ASAHI KASEI
[AK4520A]
OPERATION OVERVIEW
System Clock Input
The AK4520A with CMODE is used to select either MCLK=256fs or 384fs. The relationship between the
external clock applied to the MCLK input and the desired sample rate is defined in Table 1 . The LRCK clock
input must be synchronized with MCLK, however the phase is not critical. Internal timing is synchronized to
LRCK upon power-up or when the internal timing becomes out of phase. All external clocks must be present
unless both PWDA and PWAD ="L", otherwise excessive current may result from abnormal operation of
internal dynamic logic.
MCLK
fs
32.0kHz
44.1kHz
48.0kHz
256fs
CMODE="L"
384fs
CMODE="H"
SCLK
64fs
32fs
1.0240MHz
1.4112MHz
1.5360MHz
8.1920MHz
12.2880MHz
2.048MHz
11.2896MHz
16.9344MHz
2.822MHz
12.2880MHz
18.4320MHz
3.072MHz
Table 1 . System Clock Example
Audio Serial Interface Format
Data is shifted in/out the SDTI/SDTO pins using SCLK and LRCK inputs. Four serial data modes are
supported selected by the DIF0 and DIF1 pins as shown in Table 2 . In all modes the serial data is MSB-first,
2's compliment format is clocked on the falling edge of SCLK. For mode 3, if SCLK is 32fs, then the least
significant bits will be truncated.
Mode
0
1
2
3
DIF1
0
0
1
1
DIF0
0
1
0
1
SDTO(ADC)
20bit, MSB justified
20bit, MSB justified
20bit, MSB justified
IIS(I2S)
SDTI(DAC)
16bit, LSB justified
20bit, LSB justified
20bit, MSB justifie
IIS(I2S)
Table 2 . Serial Data Modes
L/R
H/L
H/L
H/L
L/H
SCLK
≥32fs
≥40fs
≥40fs
32fs or
≥40fs
0163-E-00
-9-
1997/3
AKM [ ASAHI KASEI MICROSYSTEMS ]
