[AK4490]
8. Electrical Characteristics
■ Analog Characteristics
(Ta=25C; AVDD=DVDD=3.3V; AVSS=DVSS=VSSL/R=0V; VREFHL/R=VDDL/R=5V, VREFLL/R=
VSSL/R=0V; Input data = 24bit; RL 1k; BICK=64fs; Signal Frequency = 1kHz; Sampling Frequency =
44.1kHz; Measurement bandwidth = 20Hz ~ 20kHz; External Circuit: Figure 41; unless otherwise specified.)
Parameter
min
typ
max
Unit
Resolution
-
-
32
Bits
Dynamic Characteristics
(Note 6)
0dBFS
60dBFS
0dBFS
60dBFS
0dBFS
60dBFS
60dBFS
fs=44.1kHz
BW=20kHz
fs=96kHz
-
-
-
-
-112
-57
-109
-54
-105
-49
-100
-44
dB
dB
dB
dB
THD+N
BW=40kHz
fs=192kHz
BW=40kHz
BW=80kHz
-106
-54
-51
120
120
123
120
-100
-44
-41
-
-
-
-
dB
dB
dB
dB
dB
dB
dB
Dynamic Range (60dBFS with A-weighted)
S/N (A-weighted)
S/N (Mono mode, A-weighted)
Interchannel Isolation (1kHz)
DC Accuracy
(Note 7)
(Note 8)
115
115
118
110
Interchannel Gain Mismatch
Gain Drift
Output Voltage
Load Capacitance
Load Resistance
-
-
0.15
-
2.8
-
-
0.3
20
2.95
25
dB
ppm/C
Vpp
pF
(Note 9)
(Note 10)
2.65
-
1
(Note 11)
-
k
Power Supplies
Power Supply Current
Normal operation (PDN pin = “H”)
VDDL/R
22
0.6
10
15
17
32
1.2
14
20
23
mA
mA
mA
mA
mA
AVDD
DVDD (fs= 44.1kHz)
DVDD (fs= 96kHz)
DVDD (fs = 192kHz)
Power down (PDN pin = “L”)
AVDD+VDDL/R+DVDD
-
-
-
(Note 12)
-
10
100
A
Note 6. Measured by Audio Precision, System Two. Averaging mode. Refer to the evaluation board manual.
Note 7. Figure 41 External LPF Circuit Example 2. 101dB for 16-bit data and 118dB for 20-bit data.
Note 8. Figure 41 External LPF Circuit Example 2. S/N does not depend on input data size.
Note 9. The voltage on (VREFH VREFL) is held +5V externally.
Note 10. Full•scale voltage(0dB). Output voltage scales with the voltage of (VREFHL/R VREFLL/R).
AOUT (typ.@0dB) = (AOUT+) (AOUT) = 2.8Vpp (VREFHL/R VREFLL/R)/5.
Note 11. Regarding Load Resistance, AC load is 1k (min) with a DC cut capacitor (Figure 41). DC load is
1.5k ohm (min) without a DC cut capacitor (Figure 40). The load resistance value is with respect to
ground. Analog characteristics are sensitive to capacitive load that is connected to the output pin.
Therefore the capacitive load must be minimized.
Note 12. In the power down mode. The PSN pin = DVDD, and all other digital input pins including clock pins
(MCLK, BICK and LRCK) are held DVSS.
MS1648-E-03
2014/11
- 10 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
