[AK4480]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=VDDL/R=4.75 ∼ 5.25V, DVDD=4.75 ∼ 5.25V)
Parameter
Symbol
min
typ
max
Unit
Master Clock Timing
Frequency
fCLK
dCLK
7.7
40
41.472
60
MHz
%
Duty Cycle
LRCK Frequency
(Note 16)
1152fs, 512fs or 768fs
fsn
fsd
fsq
30
54
108
45
54
108
216
55
kHz
kHz
kHz
%
256fs or 384fs
128fs or 192fs
Duty Cycle
Duty
PCM Audio Interface Timing
BICK Period
1152fs, 512fs or 768fs
256fs or 384fs
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
1/128fsn
1/64fsd
1/64fsq
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
128fs or 192fs
BICK Pulse Width Low
BICK Pulse Width High
BICK “↑” to LRCK Edge
LRCK Edge to BICK “↑”
SDATA Hold Time
SDATA Setup Time
30
(Note 17)
(Note 17)
20
tLRB
20
tSDH
tSDS
20
20
External Digital Filter Mode
BICK Period
tB
tBL
27
10
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
BCK Pulse Width Low
BCK Pulse Width High
BCK “↑” to WCK Edge
WCK Edge to BCK “↑”
WCK Pulse Width Low
WCK Pulse Width High
DATA Hold Time
tBH
tBW
tWB
tWCK
tWCH
tDH
5
54
54
5
tDS
5
DATA Setup Time
DSD Audio Interface Timing
DCLK Period
tDCK
tDCKL
tDCKH
tDDD
-
1/64fs
ns
ns
ns
ns
DCLK Pulse Width Low
DCLK Pulse Width High
DCLK Edge to DSDL/R
160
160
−20
(Note 18)
20
Control Interface Timing
CCLK Period
tCCK
tCCKL
tCCKH
tCDS
200
80
ns
ns
ns
ns
ns
ns
ns
ns
CCLK Pulse Width Low
Pulse Width High
80
CDTI Setup Time
50
CDTI Hold Time
tCDH
tCSW
tCSS
50
CSN High Time
150
50
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCSH
50
Reset Timing
PDN Pulse Width
(Note 19)
tPD
150
ns
MS1146-E-03
2012/01
- 12 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
