[AK4430]
■ Reset Function
When the MCLK or LRCK or BICK stops, the AK4430 is placed in reset mode and its analog outputs are set to VSS (0V,
typ). When the MCLK and LRCK, BICK are restarted, the AK4430 returns to normal operation mode.
Clock In
MCLK, BICK, LRCK
(1)
MCLK or BICK or LRCK
Stop
Internal
Normal Operation
Reset
Normal Operation
State
D/A In
(Digital)
(2)
(3)
(4)
(4)
VSS
D/A Out
(Analog)
Notes:
(1) Clocks (MCLK, BICK, LRCK) can be stopped in the reset mode (MCLK, LRCK or BICK is stopped).
(2) Digital data can be stopped. The click noise after MCLK, LRCK and BICK are input again can be reduced by
inputting the “0” data during this period.
(3) Digital data is muted for about 180/fs (in Normal speed mode) from the timing when a clock starts, and then the
analog data is output after GD.
(4) No audible click noise occurs under normal conditions.
Figure 9. Reset Timing Example
MS1196-E-01
2011/03
- 13 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
