[AK4438]
Parameter
Symbol
Min.
Typ.
Max.
Unit
Control Interface Timing (3-wire Serial mode):
CCLK Period
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
200
80
80
40
40
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “” to CCLK “”
tCSH
CCLK “” to CSN “”
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
-
400
-
-
-
-
-
-
-
1.0
0.3
-
50
400
kHz
s
s
s
s
s
s
s
s
s
ns
pF
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
(Note 18)
tF
tSU:STO
0.6
0
-
Pulse Width of Spike Noise Suppressed by Input Filter tSP
Capacitive load on bus
Power-down & Reset Timing
PDN Pulse Width
Cb
(Note 19)
tAPD
tRPD
800
ns
ns
PDN Reject Pulse Width
50
Note 18. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 19. The AK4438 can be reset by setting the PDN pin to “L” upon power-up. The PDN pin must held
“L” for more than 800ns for a certain reset. The AK4438 is not reset by the “L” pulse less than
50ns.
Note 20. I2C-bus is a trademark of NXP B.V.
016001925-E-00
2016/03
- 16 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
