[AK4426]
■ Reset Function
When the MCLK, LRCK or BICK stops, the AK4426 is placed in reset mode and its analog outputs are set to VSS (0V,
typ). When the MCLK, LRCK and BICK are restarted, the AK4426 returns to normal operation mode.
Clock In
MCLK, BICK, LRCK
(1)
MCLK or BICK or LRCK
Stop
Internal
Normal Operation
Reset
Normal Operation
State
D/A In
(Digital)
(2)
GD (3)
(4)
(4)
VSS
D/A Out
(Analog)
Notes:
(1) Clocks (MCLK, BICK, LRCK) can be stopped in the reset mode (MCLK or LRCK is stopped).
(2) Digital data can be stopped. The click noise after MCLK and LRCK are input again can be reduced by inputting
the “0” data during this period.
(3) The analog output corresponding to a specific digital input has group delay (GD).
(4) No audible click noise occurs under normal conditions.
Figure 12. Reset Timing Example
MS1176-E-02
2011/03
- 18 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
