ASAHI KASEI
[AK4388]
SYSTEM DESIGN
Figure 7 shows the system connection diagram. An evaluation board (AKD4388) is available in order to allow an easy
study on the layout of a surrounding circuit.
Optional External
Mute Circuits
Master Clock
64fs
MCLK
BICK
SDTI
DZF
1
2
3
4
5
6
7
8
16
15
DEM
Analog
Supply 5V
VDD 14
VSS 13
24bit Audio Data
fs
+
10u
0.1u
LRCK
RSTN
SMUTE
ACKS
AK4388
10u
+
Reset & Power down
VCOM
AOUTL
12
11
Lch Out
Rch Out
AOUTR 10
DIF1
Mode
Setting
DIF0
9
Digital Ground
Analog Ground
Figure 7. Typical Connection Diagram
Notes:
- LRCK = fs, BICK = 64fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
- All input pins except DIF1 and DEM pins should not be left floating.
MS0485-E-01
2006/07
- 13 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
