ASAHI KASEI
[AK4381]
n
Ordering Guide
AK4381VT
AKD4381
-40
∼
+85°C
16pin TSSOP (0.65mm pitch)
Evaluation Board for AK4381
n
Pin Layout
MCLK
BICK
SDTI
LRCK
PDN
CSN
CCLK
CDTI
1
2
3
4
5
6
7
8
16
15
14
DZFL
DZFR
VDD
VSS
AOUTL+
AOUTL-
AOUTR+
AOUTR-
Top
View
13
12
11
10
9
PIN/FUNCTION
Function
Master Clock Input Pin
An external TTL clock should be input on this pin.
2
BICK
I
Audio Serial Data Clock Pin
3
SDTI
I
Audio Serial Data Input Pin
4
LRCK
I
L/R Clock Pin
5
PDN
I
Power-Down Mode Pin
When at “L”, the AK4381 is in the power-down mode and is held in reset.
The AK4381 should always be reset upon power-up.
6
CSN
I
Chip Select Pin
7
CCLK
I
Control Data Input Pin
8
CDTI
I
Control Data Input Pin in serial mode
9
AOUTR-
O
Rch Negative Analog Output Pin
10
AOUTR+
O
Rch Positive Analog Output Pin
11
AOUTL-
O
Lch Negative Analog Output Pin
12
AOUTL+
O
Lch Positive Analog Output Pin
13
VSS
-
Ground Pin
14
VDD
-
Power Supply Pin
15
DZFR
O
Rch Data Zero Input Detect Pin
16
DZFL
O
Lch Data Zero Input Detect Pin
Note: All input pins should not be left floating.
No.
1
Pin Name
MCLK
I/O
I
MS0152-E-00
-2-
2002/5
AKM [ ASAHI KASEI MICROSYSTEMS ]
