ASAHI KASEI
[AK4370]
AVDD
AK4370
110k
LIN1 pin
HP-Amp
LIN1HL bit
100k
Note: If the path is OFF and the signal is input to the input pin, the input pin should be biased to a voltage equivalent to
VCOM voltage (= 0.475 x AVDD) externally.
Figure 39. External Bias Circuit Example for Line Input Pin
1. Grounding and Power Supply Decoupling
The AK4370 requires careful attention to power supply and grounding arrangements. AVDD and HVDD are usually
supplied from the analog power supply in the system and DVDD is supplied from AVDD via a 10Ω resistor. Alternatively
if AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or more. When
the AK4370 is powered-down, DVDD should be powered-down at the same time or later than AVDD. When AVDD and
HVDD are supplied separately, AVDD should be powered-up at the same time or earlier than HVDD. When the AK4370
is powered-down, AVDD should be powered-down at the same time or later than HVDD. VSS1 and VSS2 must be
connected to the analog ground plane. System analog ground and digital ground should be connected together near to
where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as close to the AK4370 as
possible, with the small value ceramic capacitors being the nearest.
2. Voltage Reference
The input voltage to AVDD sets the analog output range. Usually a 0.1μF ceramic capacitor is connected between AVDD
and VSS1. VCOM is a signal ground of this chip (0.475 x AVDD). The electrolytic capacitor around 2.2μF attached
between VCOM anVSS1 eliminates the effects of high frequency noise, too. No load current may be drawn from VCOM
pin. All signals, especially clock, should be kept away from AVDD and VCOM in order to avoid unwanted coupling into
the AK4370.
3. Analog Outputs
The analog outputs are single-ended outputs, and 0.48 x AVDD Vpp(typ)@−3dBFS for headphone-amp and
0.61xAVDD Vpp(typ) @0dBFS for LOUT/ROUT centered on the VCOM voltage. The input data format is 2’s
compliment. The output voltage is a positive full scale for 7FFFFFH(@24bit) and negative full scale for
800000H(@24bit). The ideal output is VCOM voltage for 000000H(@24bit).
DC offsets on the analog outputs is eliminated by AC coupling since the analog outputs have a DC offset equal to VCOM
plus a few mV.
MS0595-E-00
2007/03
- 47 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
