ASAHI KASEI
[AK4370]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, HVDD=1.6 ∼ 3.6V; CL = 20pF; unless otherwise specified)
Parameter
Symbol
min
typ
max
Units
Master Clock Input Timing
Frequency
Pulse Width Low (Note 22)
Pulse Width High (Note 22)
AC Pulse Width (Note 23)
LRCK Timing
fCLK
tCLKL
tCLKH
tACW
2.048
0.4/fCLK
0.4/fCLK
20.3
-
-
-
-
24.576
MHz
ns
ns
-
-
-
ns
Frequency
Duty Cycle: Slave Mode
Master Mode
fs
Duty
Duty
8
45
-
44.1
-
50
48
55
-
kHz
%
%
Serial Interface Timing (Note 24)
Slave Mode (M/S bit = “0”):
BICK Period (Note 25)
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
312.5 or 1/(64fs)
-
-
-
-
-
-
-
1/(32fs)
ns
ns
ns
ns
ns
ns
ns
BICK Pulse Width Low
100
100
50
50
50
-
-
-
-
-
-
Pulse Width High
LRCK Edge to BICK “↑” (Note 26)
BICK “↑” to LRCK Edge (Note 26)
SDATA Hold Time
SDATA Setup Time
50
Master Mode (M/S bit = “1”):
BICK Frequency (BF bit = “1”)
(BF bit = “0”)
BICK Duty
BICK “↓” to LRCK
SDATA Hold Time
fBCK
fBCK
dBCK
tMBLR
tSDH
-
-
-
64fs
32fs
50
-
-
-
-
-
50
-
Hz
Hz
%
ns
ns
ns
−50
50
50
SDATA Setup Time
Control Interface Timing (3-wire Serial mode)
CCLK Period
tSDS
-
-
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
200
80
80
40
40
150
50
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↑” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCSH
Note 22. Except AC coupling.
Note 23. Pulse width to ground level when MCKI is connected to a capacitor in series and a resistor is connected to
ground. (Refer to Figure 3.)
Note 24. Refer to “Serial Data Interface”.
Note 25. Min is longer value between 312.5ns or 1/(64fs) except for PLL Mode, PLL4-0 bits = “EH”, “FH”.
Note 26. BICK rising edge must not occur at the same time as LRCK edge.
MS0595-E-00
2007/03
- 11 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
