ASAHI KASEI
[AK4367]
1. Grounding and Power Supply Decoupling
The AK4367 requires careful attention to power supply and grounding arrangements. VDD and HVDD are usually
supplied from the analog power supply in the system. When VDD and HVDD are supplied separately, VDD must be
powered-up at the same time or earlier than HVDD. When the AK4367 is powered-down, HVDD must be powered-down
at the same time or later than VDD. VSS must be connected to the analog ground plane. System analog ground and digital
ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling
capacitors should be as close to the AK4367 as possible, with the small value ceramic capacitors being the nearest.
2. Voltage Reference
The input voltage to VDD sets the analog output range. A 0.1µF ceramic capacitor and a 10µF electrolytic capacitor is
connected between VDD and VSS, normally. VCOM is a signal ground of this chip (0.45 x VDD). An electrolytic 2.2µF
in parallel with a 0.1µF ceramic capacitor attached between VCOM and VSS eliminates the effects of high frequency
noise. No load current may be drawn from VCOM pin. All signals, especially clock, should be kept away from VDD and
VCOM in order to avoid unwanted coupling into the AK4367.
3. Analog Outputs
The analog outputs are single-ended outputs, and 0.47xVDD Vpp(typ)@−4.8dBFS for headphone amp and 0.66xVDD
Vpp(typ) for MOUT centered on the VCOM voltage. The input data format is 2’s compliment. The output voltage is a
positive full scale for 7FFFFFH(@24bit) and negative full scale for 800000H(@24bit). The ideal output is VCOM
voltage for 000000H(@24bit).
DC offsets on the analog outputs is eliminated by AC coupling since the analog outputs have a DC offset equal to VCOM
plus a few mV.
MS0247-E-02
2005/10
- 36 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
