ASAHI KASEI
AKM CONFIDENTIAL
[AK4366]
DC CHARACTERISTICS
(Ta=25°C; VDD, HVDD=2.2
∼
3.6V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
70%DVDD
Low-Level Input Voltage
VIL
-
Input Voltage at AC Coupling
(Note 13)
VAC
0.4
Input Leakage Current
(Note 14)
Iin
-
Note 13. Only MCLK pin. (Figure 19)
Note 14. P/S pin has internal pull-down device, nominally 100kΩ.
typ
-
-
-
-
max
-
30%DVDD
-
±10
Units
V
V
Vpp
µA
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD, HVDD=2.2
∼
3.6V; C
L
= 20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
Frequency
fCLK
2.048
-
24.576
MHz
Pulse Width Low
(Note 15)
tCLKL
0.4/fCLK
-
-
ns
Pulse Width High
(Note 15)
tCLKH
0.4/fCLK
-
-
ns
AC Pulse Width
(Note 18)
tACW
20
-
-
ns
LRCK Timing
Frequency
fs
8
44.1
48
kHz
Duty Cycle:
Duty
45
-
55
%
Serial Interface Timing
(Note 16)
BICK Period
tBCK
1/(64fs)
-
-
ns
BICK Pulse Width Low
tBCKL
130
-
-
ns
Pulse Width High
tBCKH
130
-
-
ns
(Note 17)
tLRB
50
-
-
ns
LRCK Edge to BICK “↑”
(Note 17)
tBLR
50
-
-
ns
BICK “↑” to LRCK Edge
SDATA Hold Time
tSDH
50
-
-
ns
SDATA Setup Time
tSDS
50
-
-
ns
Control Interface Timing
CCLK Period
tCCK
200
-
-
ns
CCLK Pulse Width Low
tCCKL
80
-
-
ns
Pulse Width High
tCCKH
80
-
-
ns
CDTI Setup Time
tCDS
40
-
-
ns
CDTI Hold Time
tCDH
40
-
-
ns
CSN “H” Time
tCSW
150
-
-
ns
tCSS
50
-
-
ns
CSN “↑” to CCLK “↑”
tCSH
50
-
-
ns
CCLK “↑” to CS “↑”
Note 15. Except AC coupling.
Note 16. Refer to “Serial Data Interface”.
Note 17. BICK rising edge must not occur at the same time as LRCK edge.
Note 18. Pulse width to ground level when MCLK is connected to a capacitor in series and a resistor is connected to ground.
(Refer to Figure 3.)
REV 0.6
-8-
2003/3
AKM [ ASAHI KASEI MICROSYSTEMS ]
