ASAHI KASEI
[AK4343]
Units
min
typ
max
Parameter
Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, AVOL=0dB, DVOL=0dB, RL=8Ω, BTL,
HVDD=3.3V; unless otherwise specified.
Output Voltage (Note 17)
-
3.11
3.92
3.92
-
Vpp
Vpp
Vpp
SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW)
SPKG1-0 bits = “01”, −0.5dBFS (Po=240mW)
HVDD=5V, SPKG1-0 bits = “11”, 0dBFS (Po=1W)
Line Input Æ SPP/SPN pins, HVDD=5V,
3.13
3.13
4.71
4.71
-
2.83
-
Vrms
SPKG1-0 bits = “11”,
S/(N+D)
−
1.5dBV Input (Po=1.2W)
-
20
20
60
50
30
-
-
-
dB
dB
dB
SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW)
SPKG1-0 bits = “01”, −0.5dBFS (Po=240mW)
HVDD=5V, SPKG1-0 bits = “11”, 0dBFS (Po=1W)
Line Input Æ SPP/SPN pins, HVDD=5V,
-
20
-
dB
SPKG1-0 bits = “11”,
S/N (A-weighted)
Load Resistance
−
1.5dBV Input (Po=1.2W)
80
8
90
-
-
-
dB
Ω
Load Capacitance
-
-
30
pF
Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, AVOL=0dB, DVOL=0dB, CL=3µF, Rseries=10Ω x
2, BTL, HVDD=5.0V; unless otherwise specified.
Output Voltage SPKG1-0 bits = “10”, 0dBFS
(Note 17) SPKG1-0 bits = “11”, 0dBFS
-
6.80
-
40
80
50
-
6.75
8.50
60
50
90
-
-
Vpp
Vpp
dB
dB
dB
Ω
10.20
-
-
-
-
S/(N+D)
SPKG1-0 bits = “10”, 0dBFS
(Note 18) SPKG1-0 bits = “11”, 0dBFS
(A-weighted)
S/N
Load Resistance (Note 19)
Load Capacitance (Note 19)
-
3
µF
Mono Input: MIN pin (AIN3 bit = “0”; External Input Resistance=20kΩ)
Maximum Input Voltage (Note 20)
Gain (Note 21)
-
1.98
-
Vpp
MIN Æ LOUT/ROUT
MIN Æ HPL/HPR
MIN Æ SPP/SPN
LOVL bit = “0”
0
+2
−20
−16.4
+4.5
dB
dB
dB
dB
−4.5
LOVL bit = “1”
HPG bit = “0”
HPG bit = “1”
-
−24.5
-
-
−15.5
-
ALC bit = “0”, SPKG1-0 bits = “00”
ALC bit = “0”, SPKG1-0 bits = “01”
ALC bit = “0”, SPKG1-0 bits = “10”
ALC bit = “0”, SPKG1-0 bits = “11”
ALC bit = “1”, SPKG1-0 bits = “00”
ALC bit = “1”, SPKG1-0 bits = “01”
ALC bit = “1”, SPKG1-0 bits = “10”
ALC bit = “1”, SPKG1-0 bits = “11”
+4.43
+6.43
+10.65
+12.65
+6.43
+8.43
+12.65
+14.65
+8.93
dB
dB
dB
dB
dB
dB
dB
dB
−0.07
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Note 17. Output voltage is proportional to AVDD voltage.
Vout = 0.94 x AVDD(typ)@SPKG1-0 bits = “00”, 1.19 x AVDD(typ)@SPKG1-0 bits = “01”, 2.05 x
AVDD(typ)@SPKG1-0 bits = “10”, 2.58 x AVDD(typ)@SPKG1-0 bits = “11” at Full-differential output.
Note 18. In case of measuring at SPP and SPN pins.
Note 19. Load impedance is total impedance of series resistance (Rseries) and piezo speaker impedance at 1kHz in Figure
58. Load capacitance is capacitance of piezo speaker. When piezo speaker is used, 10Ω or more series resistors
should be connected at both SPP and SPN pins, respectively.
Note 20. Maximum voltage is in proportion to both AVDD and external input resistance (Rin). Vin = 0.6 x AVDD x Rin
/ 20kΩ (typ).
Note 21. The gain is in inverse proportion to external input resistance.
MS0478-E-01
2006/10
- 10 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
