AK4343VN 参数 Datasheet PDF下载

ASAHI KASEI

[AK4343]

PIN/FUNCTION

No.

1

Pin Name

TEST1

I/O

-

Function

Test 1 Pin

This pin should be left floating.

Common Voltage Output Pin, 0.45 x AVDD

2 VCOM

O

Bias voltage of DAC outputs.

3 AVSS

-

Analog Ground Pin

4 AVDD

-

Analog Power Supply Pin

Output Pin for Loop Filter of PLL Circuit (AIN3 bit = “0”: PLL is available)

VCOC

O

5

This pin should be connected to AVSS with one resistor and capacitor in series.

RIN3

I

Rch Analog Input 3 Pin (AIN3 bit = “1”: PLL is not available)

Control Mode Select Pin

6 I2C

I

“H”: I

2

C Bus, “L”: 3-wire Serial

Power-Down Mode Pin

7 PDN

I

“H”: Power-up, “L”: Power-down, reset and initializes the control register.

CSN

I

Chip Select Pin (I2C pin = “L”: 3-wire Serial Mode)

8

CAD0

I

Chip Address 1 Select Pin (I2C pin = “H”: I

2

C Bus Mode)

CCLK

I

Control Data Clock Pin (I2C pin = “L”: 3-wire Serial Mode)

9

SCL

I

Control Data Clock Pin (I2C pin = “H”: I

2

C Bus Mode)

CDTI

I

Control Data Input Pin (I2C pin = “L”: 3-wire Serial Mode)

10

SDA

I/O Control Data Input Pin (I2C pin = “H”: I

2

C Bus Mode)

11 SDTI

I

Audio Serial Data Input Pin

Test 2 Pin

-

12 TEST2

This pin should be left floating.

13 LRCK

I/O Input / Output Channel Clock Pin

14 BICK

I/O Audio Serial Data Clock Pin

15 DVDD

-

Digital Power Supply Pin

16 DVSS

-

Digital Ground Pin

17 MCKI

I

External Master Clock Input Pin

18 MCKO

O

Master Clock Output Pin

19 SPN

O

Speaker Amp Negative Output Pin

20 SPP

O

Speaker Amp Positive Output Pin

21 HVDD

-

Headphone & Speaker Amp Power Supply Pin

22 HVSS

-

Headphone & Speaker Amp Ground Pin

23 HPR

O

Rch Headphone-Amp Output Pin

24 HPL

O

Lch Headphone-Amp Output Pin

Mute Time Constant Control Pin

25 MUTET

O

Connected to HVSS pin with a capacitor for mute time constant.

ROUT

O

Rch Stereo Line Output Pin (RCV bit = “0”: Single-ended Stereo Output)

26

RCN

O

Receiver-Amp Negative Output Pin (RCV bit = “1”: BTL output)

LOUT

O

Lch Stereo Line Output Pin (RCV bit = “0”: Single-ended Stereo Output)

27

RCP

O

Receiver-Amp Positive Output Pin (RCV bit = “1”: BTL output)

MIN

I

Mono Signal Input Pin (AIN3 bit = “0”: PLL is available)

28

LIN3

I

Lch Analog Input 3 Pin (AIN3 bit = “1”: PLL is not available)

RIN2

I

Rch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input)

29

I

Rch Negative Input 2 Pin (MDIF2 bit = “1”: Full-differential Input)

IN2−

LIN2

I

Lch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input)

30

IN2+

I

Rch Positive Input 2 Pin (MDIF2 bit = “1”: Full-differential Input)

LIN1

I

Lch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input)

31

I

Lch Negative Input 1 Pin (MDIF1 bit = “1”: Full-differential Input)

IN1−

RIN1

I

Rch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input)

32

IN1+

I

Lch Positive Input 1 Pin (MDIF1 bit = “1”: Full-differential Input)

Note 1. All input pins except analog input pins (MIN/LIN3, LIN1, RIN1, LIN2, RIN2, RIN3) should not be left floating.

Note 2. AVDD or AVSS voltage should be input to I2C pin.

MS0478-E-01

-5-

2006/10