ASAHI KASEI
[AK4319A]
2. Voltage reference
The on-chip voltage reference is output on the VREF pin. An electrolytic capacitor smaller than 10uF in
parallel with a 0.1uF ceramic capacitor attached to this pin eliminates the effects of high frequency noise.
Especially, the ceramic capacitor should be connected to VREF pin within a few mm as near as possible.
No load current may be taken from the VREF output pin. All signals, especially clocks, should be kept
away from the VREF pin in order to avoid unwanted coupling into the AK4319A.
3. Analog Outputs
The analog signals are output from the differential output pins of each channel, therefore they are
summed externally.The analog outputs are the differential voltage,∆VAOUT=(AOUT+)-(AOUT-) between
AOUT+ and AOUT-.The bias voltage(Vop/2) for this summing circuit is supplied externally.The output
signal range is ±1.40V(0.99Vrms, typ) centered at an internal common voltage(AVDD/2). If the summing
gain is 1, the output range is ±2.80V (1.98Vrms, typ).The input data format is 2's complement.The
output voltage(∆VAOUT) is a positive full scale for 7FFFH(@16bit) and a negative full scale for
8000H(@16bit).The ideal ∆VAOUT is 0V for 0000H(@16bit).
DC offsets on analog outputs are eliminated by AC coupling the signals since DAC outputs have a few
mV offsets.
The noise generated by the delta-sigma modulator beyond the audio passband is sufficiently attenuated
by the high speed over-sampling and by the on-chip SCF filter. However, as the outband noise moves
into the audible band at low sampling rate, careful attention is required. On Figure 9 , the differential
outputs of AK4319A are summed by the
1st-order LPF and the 1.98Vrms output signal range is acquired.
Figure 9 . External LPF example
M0011-E-01
1998/6
- 14 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
