ASAHI KASEI
[AK4317]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD,DVDD=4.5∼5.5V; C
L
=20pF)
Parameter
Master Clock Timing
256fs:
Pulse Width Low
Pulse Width High
384fs:
Pulse Width Low
Pulse Width High
Symbol
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fs
Duty
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tPD
min
2.048
28
28
3.072
23
23
8
45
312.5
100
100
50
50
50
50
100
100
50
50
100
50
50
150
44.1
typ
max
12.8
Unit
MHz
ns
ns
MHz
ns
ns
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
19.2
LRCK
Frequency
Duty Cycle
Serial Interface Timing
BICK Period
BICK Pulse Width Low
Pulse Width High
BICK rising to LRCK edge (Note 12 )
LRCK Edge to BICK rising (Note 12 )
SDATA Hold Time
SDATA Setup Time
Control Interface Timing
CCLK Pulse Width Low
Pulse Width High
CDATA Latch Hold Time
CDATA Latch Setup Time
CS Pulse Width Low
CCLK to CS falling
CS rising to CCLK
Reset Timing
PD Pulse Width
(Note 13 )
50
55
Notes: 12. BICK rising edge must not occur at the same time as LRCK edge.
13. The AK4317 can be reset by bringing PD "L" to "H" only upon power up.
0172-E-01
-7-
1997/5
AKM [ ASAHI KASEI MICROSYSTEMS ]
