[AK4223]
R1
75 Ω
VOUT
R2
75 Ω
C1
C2
max: 15pF
(C2)
max:1.5nF
(C1)
Figure 4. Load Resistance R1+R2 and Load Capacitance C1/C2 (VR1/2 bit = “0”)
R1
C
100kΩ (min)
VOUT
C1
C2
C1+C2=15pF (max)
Figure 5. Load Resistance R1+R2 and Load Capacitance C1/C2 (VR1/2 bit = “1”)
DC CHARACTERISTICS
(Ta=-40~85°C; AVDD= RVDD= VVDD= 7.5∼9.5V)
Parameter
Symbol
VIH
VIL
min
2.7
-
typ
max
5.5
0.8
Units
V
V
High-Level Input Voltage (RSTN,SCL,SDA,CAD pins)
Low-Level Input Voltage (RSTN,SCL,SDA,CAD pins)
-
-
Low-Level Output Voltage (SDA pin: Iout=3mA)
Input Leakage Current
VOL
Iin
-
-
-
-
0.4
V
±10
μA
SWITCHING CHARACTERISTICS
(Ta= 25°C; AVDD =RVDD= VVDD= 9.0V)
Control Interface Timing (I2C Bus)
SCL Clock Frequency
fSCL
tBUF
-
400
-
-
-
-
-
-
-
0.3
0.3
-
50
400
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
(Note 13)
tF
tSU:STO
tSP
Cb
0.6
0
-
Pulse Width of Spike Noise Suppressed by Input Filter
Capacitive load on bus
pF
Power-down & Reset Timing
RSTN Reject Pulse Width
tRPD
tPD
15
ns
ns
RSTN Pulse Width
(Note 14)
150
Note 12. I2C-bus is a trademark of NXP B.V.
Note 13. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 14. The AK4223 can be reset by setting the RSTN pin = “L” when powered up.
MS1251-E-00
9
2010/10
AKM [ ASAHI KASEI MICROSYSTEMS ]
