[AK4223]
R1
75
Ω
VOUT
C2
max: 15pF
(C2)
C1
max:1.5nF
(C1)
R2
75
Ω
Figure 4. Load Resistance R1+R2 and Load Capacitance C1/C2 (VR1/2 bit = “0”)
C
VOUT
C2
C1
R1
100kΩ (min)
C1+C2=15pF (max)
Figure 5. Load Resistance R1+R2 and Load Capacitance C1/C2 (VR1/2 bit = “1”)
DC CHARACTERISTICS
(Ta=-40~85°C; AVDD= RVDD= VVDD= 7.5∼9.5V)
Parameter
Symbol
min
High-Level Input Voltage (RSTN,SCL,SDA,CAD pins)
VIH
2.7
Low-Level Input Voltage (RSTN,SCL,SDA,CAD pins)
VIL
-
Low-Level Output Voltage (SDA pin: Iout=3mA)
VOL
-
Input Leakage Current
-
Iin
typ
-
-
-
-
max
5.5
0.8
0.4
±10
Units
V
V
V
μA
SWITCHING CHARACTERISTICS
(Ta= 25°C; AVDD =RVDD= VVDD= 9.0V)
Control Interface Timing (I
2
C Bus)
SCL Clock Frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
Capacitive load on bus
Cb
-
Power-down & Reset Timing
RSTN Reject Pulse Width
tRPD
RSTN Pulse Width
tPD
150
2
Note 12. I C-bus is a trademark of NXP B.V.
Note 13. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 14. The AK4223 can be reset by setting the RSTN pin = “L” when powered up.
400
-
-
-
-
-
-
-
0.3
0.3
-
50
400
15
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
pF
ns
ns
MS1251-E-00
9
2010/10
AKM [ ASAHI KASEI MICROSYSTEMS ]
