I
[AK4220]
PIN/FUNCTION
No.
1
2
Pin Name
RIN+7
PDN
CAD1
CSN
SCL
CCLK
SDA
CDTI
CAD0
CDTO
INT
Q0
Q1
Q2
Q3
Q4
DVDD
DVSS
VOUT1
VFB1
TEST
VOUT2
VFB2
VVDD2
VOUT3
VFB3
VVSS2
VIN1
VVSS3
VIN2
VVDD1
VIN3
VVSS1
VIN4
IICN
VIN5
VIN6
AVDD
I/O
I
I
I
I
I
I
I/O
I
I
O
O
O
O
O
O
O
-
-
O
I
I
O
I
-
O
I
-
I
-
I
-
I
-
I
I
I
I
-
Function
Rch Audio Positive Input 7
Power down Mode
“L”: Power down, Reset
“H”: Power up
The AK4220 should always be reset upon power-up.
Chip Address1 (IICN pin = “L”)
Chip Selector (IICN pin = “H”)
Control Clock Input (IICN pin = “L”)
Control Clock Input (IICN pin = “H”)
Control Data Input/Output (IICN pin = “L”)
Control Data Input (IICN pin = “H”)
Chip Address0 (IICN pin = “L”)
Control Data Output (IICN pin = “H”)
Interrupt
Parallel Output 0 (open drain output)
Parallel Output 1 (open drain output)
Parallel Output 2 (open drain output)
Parallel Output 3 (open drain output)
Parallel Output 4 (open drain output)
Digital Power Supply
Normally connected to DVSS with a 0.1μF ceramic capacitor in parallel
with a 10μF electrolytic capacitor.
Digital Ground
Video Output 1
Video Feedback 1
Test pin, Connected to VVSS.
Video Output 2
Video Feedback 2
Video Power Supply, 5V
Normally connected to VVSS with a 0.1μF ceramic capacitor in parallel
with a 10μF electrolytic capacitor.
Video Output 3
Video Feedback 3
Video Ground2, 0V
Video Input 1
Video Ground3, 0V
Video Input 2
Video Power Supply, 5V
Normally connected to VVSS with a 0.1μF ceramic capacitor in parallel
with a 10μF electrolytic cap.
Video Input 3
Video Ground1, 0V
Video Input 4
Control Mode Selection
“L”(Connected to VVSS): IIC Bus
“H” (Connected to VVDD): 4-wire Serial
Video Input 5
Video Input 6
Audio Power Supply, 5V
Normally connected to AVSS with a 0.1μF ceramic capacitor in parallel
with a 10μF electrolytic capacitor.
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
MS0627-E-00
-5-
2007/05
AKM [ ASAHI KASEI MICROSYSTEMS ]
