[AK4205]
■ DC Characteristics
(Ta = -40 ~ 85 C; PVDDA = PVDDB = RVDD = 4.5 V ~ 6.5 V, PVEEA = PVEEB = -4.5 V ~ -5.5 V,
SWVDD = 3.0 V ~ 3.6 V; AVSSA = AVSSB = RVSS = SWVSS = 0 V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
SEL, MUTEN, RSTN pins
High-Level Input Voltage
Low-Level Input Voltage
Input Rising Time
VIH
VIL
Tr
1.44
-
-
-
-
V
V
ns
ns
0.36
20
20
Input Falling Time
Tf
Input Leakage Current
Iin
-
-
0.5
μA
Hi-Fi Mode (SEL pin = “H”)
AUX Mode (SEL pin = “L”)
2.37
1.3
2.5
1.4
2.63
1.5
V
V
Output Voltage
(CAPSS pin)
■ Switching Characteristics
(Ta = -40 ~ 85 C; PVDDA = PVDDB = RVDD = 4.5 V ~ 6.5 V, PVEEA = PVEEB = -4.5 V ~ -5.5 V,
SWVDD = 3.0 V ~ 3.6 V; AVSSA = AVSSB = RVSS = SWVSS = 0 V)
Parameter (Figure 7)
Symbol
Min.
Typ.
Max.
Unit
Soft Start Timing (RL=32Ω,Css=0.1μF: Note 33)
Turn-on Time
Turn-off Time
Turn-on slope (Vin = 20 mV)
Turn-off slope (offset Vin = 20 mV)
Reset Timing (RSTN pin: Note 33)
RSTN Pulse Width (Css = 0.1 μF)
tON
tOFF
tslON
tslOFF
59
29
1.0
1.0
ms
ms
V/s
V/s
tRST
2
-
-
ms
Note 33. Css is a capacitor connected with the CAPSS pin.
■ Headphone-amp Power-up/down Timing
Parameter (Figure 9)
Symbol
PUSLDD
PUSLEE
PDSLDD
PDSLEE
tPU
Min.
Typ.
Max.
15
-
-
260
-
-
Unit
mV/μs
mV/μs
mV/μs
mV/μs
ms
VDD Power up Slope (Note 34)
VEE Power up Slope (Note 35)
VDD Power down Slope (Note 34, Note 36)
VEE Power down Slope (Note 35, Note 36)
VDD-VEE non-overlap Time
-
-50
-100
-
0
0
-
-
-
-
-
-
VEE-VDD non-overlap Time
tPD
ms
Note 34. RVDD, PVDDA, PVDDB pins
Note 35. PVEEA, PVEEB pins
Note 36. At power down, set the absolute value of the voltages of RVDD, PVDDA and PVDDB so that
they do not fall below the absolute value of the voltage of PVEEA and PVEEB.
016012367-E-00
2016/12
- 11 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
