[AK4183]
■
Digital I/F
The AK4183 operates with uP via I
2
C bus and supports the standard mode (100 KHz) and the fast mode (400KHz).
Note that the AK4183 operates in those two modes and does not support a High speed mode I
2
C-bus system (3.4MHz).
The AK4183 can operate as the slave device on the I
2
C bus network.
VCC=2.5V – 3.6V
CAD0
Micro-
Processor
I
2
C bus
controller
SCL
SDA
Rp
Rp
VCC
AK4183
“L” or “H”
PENIRQN
Figure 4. Digital I/F
[Start Condition and Stop Condition]
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. All sequences start by
the START condition or Repeated Start Condition. Repeated Start condition is the same signal tradition as Start
condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All sequences are
terminated by the STOP or Repeated Start condition. Repeated Start is also the Start condition of next transfer so that
I2C bus cannot be idle.
SDA
SCL
S/Sr
S : Start condition
Sr : Repeated start condition
P : stop condition
Figure 5. START and STOP Conditions
[Data Transfer]
All commands are preceded by a START condition. After the START condition, a slave address is sent. After the
AK4183 recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted
over the SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave
device pulls the SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition
generated by the master device.
MS0500-E-01
8
2008/12
AKM [ ASAHI KASEI MICROSYSTEMS ]
