[AK4186]
S
T
A
R
T
S
T
O
P
R/W= “0”
Slave
Address
Sub
Address(n)
S
Data (n)
Data (n+1)
Data (n+x)
SDA
P
Figure 7. Data Transfer Sequence at the I2C-Bus Mode
1
0
0
1
0
0
CAD0
R/W
(This CAD0 should match with CAD0 pin.)
Figure 8. The First Byte
0
0
A5
A4
A3
A2
A1
D1
A0
D0
Figure 9. The Second Byte
D7
D6
D5
D4
D3
D2
Figure 10. Byte Structure after the second byte
SDA
SCL
S
P
start condition
stop condition
Figure 11. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
8
SCL FROM
MASTER
2
1
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 12. Acknowledge on the I2C-Bus
MS1068-E-04
2011/03
- 12 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
