[AK4186]
SWITCHING CHARACTERISTICS
(Ta=-40°C to 85°C, VDD=1.6V to 3.6V)
Parameter
Symbol
min
Internal OSCILATOR
Clock Frequency
f
OSC
2.5
Touch Panel (A/D Converter)
SCL clock frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first Clock pulse)
tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling (Note
7)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise Suppressed By Input Filter
tSP
0
Capacitive load on bus
Cb
-
Note 7: Data must be held for sufficient time to bridge the 300ns transition time of SCL.
typ
3.6
-
-
-
-
-
-
-
-
-
-
-
-
-
max
5.1
400
-
-
-
-
-
-
-
0.3
0.3
-
50
400
Units
MHz
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
pF
SDA
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
VIL
SCL
tHD:STA
Stop
Start
tHD:DAT
tSU:DAT
tSU:STA
Start
tSU:STO
Stop
VIH
VIL
Figure 2. Timing Diagram
MS1068-E-04
-6-
2011/03
AKM [ ASAHI KASEI MICROSYSTEMS ]
