[AK4186]
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 13. Bit Transfer on the I2C-Bus
2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4186.
(1) Register READ Operation
After transmission of data, the master can read the next address’s data by generating an acknowledge instead of
terminating the write cycle after the receipt of the first data word. After receiving each data packet the internal 6-bit
address counter is incremented by one, and the next data is automatically taken into the next address. If the address
exceeds 1FH prior to generating stop condition, the address counter will “roll over” to 00H and the data of 00H will be
read out. The register read operation allows the master to access any memory location at random. Prior to issuing the
slave address with the R/W bit “1”, the master must first perform a “dummy” write operation. The master issues a start
request, a slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged,
the master immediately reissues the start request and the slave address with the R/W bit “1”. The AK4186 then
generates an acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not
generate an acknowledge but generates stop condition instead, the AK4186 ceases transmission. A/D conversion data in
sequence mode can be read when the data is available.
S
T
A
R
T
S
T
A
R
T
S
T
O
P
R/W= “0”
R/W= “1”
Slave
Address
Sub
Address(n)
Slave
Address
S
S
Data (n)
Data (n+1)
Data (n+x)
P
SDA
Figure 14. Register Address Read
(2) A/D Measurement Operation
When the master send a READ command after sending a control register address for a measurement channel by a
WRITE operation, the AK4186 starts A/D conversion in single mode. The master issues the slave address with the R/W
bit “1”. The AK4186 then generates an acknowledge, and outputs ADC data. The ADC data is 2 bytes format (MSB
first), and upper 12-bit are valid and lower 4-bit are filled with “0”. (Figure 17, Figure 18) The master receives the first
byte, and generates an acknowledge. Then the master receives the second byte and does not generate an acknowledge,
the AK4186 ceases transmission. (Figure 15) If the master generates an acknowledge, the AK4186 newly repeats A/D
conversion to set the channel every read cycle, and the master can receive update ADC data on each read operation. The
AK4186 repeats A/D conversion and continuously outputs ADC data until the master does not generate an acknowledge
but generates a stop condition instead. (Figure 16) This continuous read mode enables the higher sampling rate and
lower processor load than a single ADC data read.
MS1068-E-04
2011/03
- 13 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
