ASAHI KASEI
[AK4140]
Parameter
Symbol
min
typ
max
Units
Audio Interface Timing (Master mode)
Normal mode (TDM1=“L”, TDM0=“L”)
SCLK Frequency
fBCK
dBCK
tMBLR
tBSD
64fs
50
Hz
%
SCLK Duty
SCLK “↓” to LRCK
SCLK “↓” to SDTO
−20
−40
20
40
ns
ns
TDM256 mode (TDM1=“L”, TDM0=“H”)
SCLK Frequency
fBCK
dBCK
tMBLR
tBSD
256fs
50
Hz
%
SCLK Duty
(Note 7)
SCLK “↓” to LRCK
SCLK “↓” to SDTO
TDMIN Hold Time
TDMIN Setup Time
−12
−20
10
12
20
ns
ns
ns
ns
tSDH
tSDS
10
TDM128 mode (TDM1=“H”, TDM0=“H”)
SCLK Frequency
fBCK
dBCK
tMBLR
tBSD
128fs
50
Hz
%
SCLK Duty
SCLK “↓” to LRCK
SCLK “↓” to SDTO
TDMIN Hold Time
−12
−20
10
12
20
ns
ns
ns
ns
tSDH
tSDS
TDMIN Setup Time
10
Power-Down & Reset Timing
PDN Pulse Width
(Note 8)
(Note 9)
tPD
150
ns
PDN “↑” to SDTO valid
tPDV
516
1/fs
Note 6. SCLK rising edge must not occur at the same time as LRCK edge.
Note 7. This value is MCLK=512fs. Duty cycle is not guaranteed when MCLK=256fs/384fs.
Note 8. The AK4140 can be reset by bringing the PDN pin = “L”.
Note 9. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
Parameter
Symbol
Min
typ
max
Units
Control Interface Timing (I2C Bus):
SCL Clock Frequency
fSCL
tBUF
tHD:STA
-
1.3
0.6
400
-
-
kHz
μs
μs
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first clock pulse)
Clock Low Time
Clock High Time
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
1.3
0.6
0.6
0
0.1
-
-
0.6
0
-
-
-
-
-
0.3
0.3
-
μs
μs
μs
μs
μs
μs
μs
μs
ns
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 10)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise
Suppressed by Input Filter
tF
tSU:STO
tSP
50
Capacitive load on bus
Cb
0
400
pF
Note 10. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
MS0547-E-01
2007/03
- 8 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
