ASAHI KASEI
[AK4140]
Parameter
Audio Interface Timing (Master mode)
Normal mode (TDM1=“L”, TDM0=“L”)
SCLK Frequency
SCLK Duty
SCLK “↓” to LRCK
SCLK “↓” to SDTO
TDM256 mode (TDM1=“L”, TDM0=“H”)
SCLK Frequency
SCLK Duty
SCLK “↓” to LRCK
SCLK “↓” to SDTO
TDMIN Hold Time
TDMIN Setup Time
TDM128 mode (TDM1=“H”, TDM0=“H”)
SCLK Frequency
SCLK Duty
SCLK “↓” to LRCK
SCLK “↓” to SDTO
TDMIN Hold Time
TDMIN Setup Time
Power-Down & Reset Timing
PDN Pulse Width
PDN “↑” to SDTO valid
Symbol
min
typ
max
Units
fBCK
dBCK
tMBLR
tBSD
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
tPD
tPDV
64fs
50
−20
−40
256fs
50
−12
−20
10
10
128fs
50
−12
−20
10
10
150
516
12
20
12
20
20
40
Hz
%
ns
ns
Hz
%
ns
ns
ns
ns
Hz
%
ns
ns
ns
ns
ns
1/fs
Note 6. SCLK rising edge must not occur at the same time as LRCK edge.
Note 7. This value is MCLK=512fs. Duty cycle is not guaranteed when MCLK=256fs/384fs.
Note 8. The AK4140 can be reset by bringing the PDN pin = “L”.
Note 9. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
Parameter
Control Interface Timing (I
2
C Bus):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 10)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise
Suppressed by Input Filter
Capacitive load on bus
Symbol
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
Cb
Min
-
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
0.6
0
0
typ
max
400
-
-
-
-
-
-
-
0.3
0.3
-
50
400
Units
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
pF
Note 10. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
MS0547-E-01
-8-
2007/03
AKM [ ASAHI KASEI MICROSYSTEMS ]
