ASAHI KASEI
[AK4140]
SYSTEM DESIGN
Figure 25 shows the system connection diagram. An evaluation board is available which demonstrates application
circuits, the optimum layout, power supply arrangements and measurement results.
2.2n
TST2
TST1
TSTI2
TSTI1
TSTO
PDN
FILT
10u
0.1u
AVSS
+3.3V Analog
4.5MHz SIF
AVDD
SIF
68n
DVSS
DVDD
SDTO
SCLK
LRCK
AK4140
0.1u
+3.3V Digital
INT1
INT0
fs
+3.3V Digital
uP
CAD1
CAD0
SCL
DSP
MS
10kohm
10kohm
TDMIN
256fs
MCLK
SDA
Figure 25. System Connection Example (CAD1/0 bit = “00”, Master Mode, Normal (Non-TDM) Mode.
MS0547-E-01
2007/03
- 40 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
