[AK4127]
PIN/FUNCTION
No. Pin Name
I/O
O
Function
1
2
FILT
PLL Loop Filter Pin, Hi-Z when PDN pin = “L”.
Analog Ground Pin
AVSS
-
Power-Down Mode Pin
3
4
5
PDN
I
I
“H”: Power up, “L”: Power down reset and initializes the control register.
Soft Mute Pin
SMUTE
DITHER
“H” : Soft Mute, “L” : Normal Operation
Dither Enable Pin
I
I
“H” : Dither ON, “L” : Dither OFF
PLL Mode Select 2 Pin
6
7
8
9
PLL2
ILRCK
IBICK
SDTI
I/O Input Channel Clock Pin, Output “L” when PDN = “L” and master mode.
I/O Audio Serial Data Clock Pin, Output “L” when PDN = “L” and master mode.
I
I
Audio Serial Data Input Pin
10 IDIF0
Audio Interface Format 0 Pin for Input PORT
Audio Interface Format 1 Pin for Input PORT
Audio Interface Format 2 Pin for Input PORT
PLL Mode Select 0 Pin
11 IDIF1
I
12 IDIF2
I
13 PLL0
I
14 PLL1
I
PLL Mode Select 1 Pin
15 UNLOCK
16 OBIT0
17 OBIT1
18 IMCLK
19 CMODE0
20 CMODE1
21 CMODE2
22 ODIF0
23 ODIF1
24 SDTO
O
I
Unlock Status Pin, Output “H” when PDN = “L”
Bit Length Select 0 Pin for Output Data
Bit Length Select 1 Pin for Output Data
Master Clock Input Pin for Input PORT
Clock Mode Select 0 Pin
I
I
I
I
Clock Mode Select 1 Pin
I
Clock Mode Select 2 Pin
I
Audio Interface Format 0 Pin for Output PORT
Audio Interface Format 1 Pin for Output PORT
Audio Serial Data Output Pin for Output PORT, Output “L” when PDN pin = “L”
Audio Serial Data Clock Pin for Output PORT
Output “L” when PDN = “L” and master mode.
Output Channel Clock Pin for Output PORT
Output “L” when PDN = “L” and master mode.
Master Clock/TDM Data Input Pin for Output PORT
OMCLK: Master Clock Input Pin (except for PLL2/1/0 pin = “L/H/H”)
TDMIN: TDM Data Input Pin (PLL2/1/0 pin = “L/H/H”)
Digital Power Supply Pin, 3.0 ∼ 3.6V
I
O
25 OBICK
26 OLRCK
I/O
I/O
27 OMCLK
I
28 DVDD
29 DVSS
30 AVDD
-
-
-
Digital Ground Pin
Analog Power Supply Pin, 3.0 ∼ 3.6V
Note: All input pins must not be left floating.
MS0593-E-01
2007/07
- 5 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
