ASAHI KASEI
[AK4122]
PIN/FUNCTION
No.
1
2
3
4
5
6
7
8
9
10
11
Pin Name
CDTI
CDTO
TST1
INT2
TST2
TST3
M/S2
M/S3
SMUTE
TST4
TST5
I/O
I
O
O
O
O
I
I
I
I
I
I
Function
Control Data Input Pin
Control Data Output Pin
Test 1 Pin
Interrupt 2 Pin
Test 2 Pin
Test 3 Pin
This pin should be connected to DVSS.
Master / Slave Mode Pin for PORT2
“H” : Master mode, “L” : Slave Mode
Master / Slave Mode Pin for PORT3
“H” : Master mode, “L” : Slave Mode
Soft Mute Pin
“H” : Soft Mute, “L” : Normal Operation
Test 4 Pin
This pin should be connected to AVSS.
Test 5 Pin
This pin should be connected to AVSS.
PLL Loop Filter Pin
470Ω±5% resistor and 2.2µF±50% ceramic capacitor in parallel with a
2.2nF±50% ceramic capacitor should be connected to AVSS externally.
Analog Ground Pin
Analog Power Supply Pin, 3.0
∼
3.6V
Test 6 Pin
This pin should be connected to AVSS.
Receiver Input 1 Pin with Amp for 0.2Vpp (Internal Biased Pin)
Test 7 Pin
This pin should be connected to AVSS.
Receiver Input 2 Pin with Amp for 0.2Vpp (Internal Biased Pin)
Test 8 Pin
This pin should be connected to AVSS.
Receiver Input 3 Pin with Amp for 0.2Vpp (Internal Biased Pin)
Test 9 Pin
This pin should be connected to AVSS.
Receiver Input 4 Pin with Amp for 0.2Vpp (Internal Biased Pin)
Test 10 Pin
This pin should be connected to AVSS.
Test 11 Pin
12
13
14
15
16
17
18
19
20
21
22
23
24
FILT
AVSS
AVDD
TST6
RX1
TST7
RX2
TST8
RX3
TST9
RX4
TST10
TST11
O
-
-
I
I
I
I
I
I
I
I
I
O
Note: All input pins except internal biased pins should not be left floating.
MS0267-E-02
-4-
2004/07
AKM [ ASAHI KASEI MICROSYSTEMS ]
