ASAHI KASEI
No. Pin Name
[AK4122]
PIN/FUNCTION
I/O
I
Function
1
2
3
4
5
CDTI
CDTO
TST1
INT2
TST2
Control Data Input Pin
O
O
O
O
Control Data Output Pin
Test 1 Pin
Interrupt 2 Pin
Test 2 Pin
Test 3 Pin
6
7
8
9
TST3
I
I
I
I
I
I
This pin should be connected to DVSS.
Master / Slave Mode Pin for PORT2
“H” : Master mode, “L” : Slave Mode
Master / Slave Mode Pin for PORT3
“H” : Master mode, “L” : Slave Mode
Soft Mute Pin
M/S2
M/S3
SMUTE
“H” : Soft Mute, “L” : Normal Operation
Test 4 Pin
10 TST4
11 TST5
This pin should be connected to AVSS.
Test 5 Pin
This pin should be connected to AVSS.
PLL Loop Filter Pin
12 FILT
O
470Ω±5% resistor and 2.2µF±50% ceramic capacitor in parallel with a
2.2nF±50% ceramic capacitor should be connected to AVSS externally.
Analog Ground Pin
13 AVSS
14 AVDD
-
-
Analog Power Supply Pin, 3.0 ∼ 3.6V
Test 6 Pin
15 TST6
16 RX1
17 TST7
18 RX2
19 TST8
20 RX3
21 TST9
22 RX4
23 TST10
24 TST11
I
I
This pin should be connected to AVSS.
Receiver Input 1 Pin with Amp for 0.2Vpp (Internal Biased Pin)
Test 7 Pin
I
This pin should be connected to AVSS.
Receiver Input 2 Pin with Amp for 0.2Vpp (Internal Biased Pin)
Test 8 Pin
I
I
This pin should be connected to AVSS.
Receiver Input 3 Pin with Amp for 0.2Vpp (Internal Biased Pin)
Test 9 Pin
I
I
This pin should be connected to AVSS.
Receiver Input 4 Pin with Amp for 0.2Vpp (Internal Biased Pin)
Test 10 Pin
I
I
This pin should be connected to AVSS.
Test 11 Pin
O
Note: All input pins except internal biased pins should not be left floating.
MS0267-E-02
2004/07
- 4 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
