[AK4122A]
PIN/FUNCTION
No.
1
2
3
4
5
Pin Name
CDTI
CDTO
TST1
INT2
TST2
I/O
I
O
O
O
O
Function
Control Data Input Pin
Control Data Output Pin
Test 1 Pin
Interrupt 2 Pin
Test 2 Pin
Test 3 Pin
6 TST3
I
This pin should be connected to DVSS.
Master / Slave Mode Pin for PORT2
7 M/S2
I
“H” : Master mode, “L” : Slave Mode
Master / Slave Mode Pin for PORT3
8 M/S3
I
“H” : Master mode, “L” : Slave Mode
Soft Mute Pin
9 SMUTE
I
“H” : Soft Mute, “L” : Normal Operation
Test 4 Pin
10 TST4
I
This pin should be connected to AVSS.
Test 5 Pin
11 TST5
I
This pin should be connected to AVSS.
PLL Loop Filter Pin
12 FILT
O
470Ω±5% resistor and 2.2μF±50% ceramic capacitor in parallel with a
2.2nF±50% ceramic capacitor should be connected to AVSS externally.
13 AVSS
-
Analog Ground Pin
14 AVDD
-
Analog Power Supply Pin, 3.0
∼
3.6V
Test 6 Pin
15 TST6
I
This pin should be connected to AVSS.
16 RX1
I
Receiver Input 1 Pin with Amp for 0.2Vpp (Internal Biased Pin)
Test 7 Pin
17 TST7
I
This pin should be connected to AVSS.
18 RX2
I
Receiver Input 2 Pin with Amp for 0.2Vpp (Internal Biased Pin)
Test 8 Pin
19 TST8
I
This pin should be connected to AVSS.
20 RX3
I
Receiver Input 3 Pin with Amp for 0.2Vpp (Internal Biased Pin)
Test 9 Pin
21 TST9
I
This pin should be connected to AVSS.
22 RX4
I
Receiver Input 4 Pin with Amp for 0.2Vpp (Internal Biased Pin)
Test 10 Pin
23 TST10
I
This pin should be connected to AVSS.
24 TST11
O
Test 11 Pin
Note: All input pins except internal biased pins should not be left floating.
MS1076-E-01
-4-
2010/05
AKM [ ASAHI KASEI MICROSYSTEMS ]
