[AK4122A]
External Resistor Pin
12kΩ±5% resistor should be connected to AVSS externally.
26 AVSS
-
Analog Ground Pin
Power-Down Mode Pin
27 PDN
I
“H”: Power up, “L”: Power down reset and initializes the control register.
28 LRCK1
I
Input Channel Clock Pin
29 BICK1
I
Audio Serial Data Clock Pin
30 SDTI
I
Audio Serial Data Input Pin
31 DVSS
-
Digital Ground Pin
32 DVDD
-
Digital Power Supply Pin, 3.0
∼
3.6V
33 MCLK2
I
Master Clock Input Pin
34 LRCK2
I/O Input / Output Channel Clock Pin
35 BICK2
I/O Audio Serial Data Clock Pin
36 SDTIO
I/O Audio Serial Data Input / Output Pin
37 INT0
O
Interrupt 0 Pin
38 INT1
O
Interrupt 1 Pin
39 TX
O
Transmitter Output Pin
40 SDTO
O
Audio Serial Data Output Pin
41 BICK
I/O Audio Serial Data Clock Pin
42 LRCK
I/O Output Channel Clock Pin
43 OMCLK
I
Master Clock Input Pin
44 DVSS
-
Digital Ground Pin
45 DVDD
-
Digital Power Supply Pin, 3.0
∼
3.6V
Substrate Ground Pin
46 BVSS
-
This pin should be connected to AVSS.
47 CSN
I
Chip Select Pin
48 CCLK
I
Control Data Clock Pin
Note: All input pins except internal biased pins should not be left floating.
25
R
-
MS1076-E-01
-5-
2010/05
AKM [ ASAHI KASEI MICROSYSTEMS ]
