ASAHI KASEI
[AK4120]
Parameter
Symbol
min
Control Interface Timing (3-wire Serial mode):
CCLK Period
200
tCCK
CCLK Pulse Width Low
80
tCCKL
Pulse Width High
80
tCCKH
CDTI Setup Time
40
tCDS
CDTI Hold Time
40
tCDH
CSN “H” Time
150
tCSW
50
tCSS
CSN “↓” to CCLK “↑”
50
tCSH
CCLK “↑” to CSN “↑”
Control Interface Timing (I
2
C® Bus mode):
-
fSCL
SCL Clock Frequency
4.7
tBUF
Bus Free Time Between Transmissions
4.0
tHD:STA
Start Condition Hold Time (prior to first clock pulse)
4.7
tLOW
Clock Low Time
4.0
tHIGH
Clock High Time
4.7
tSU:STA
Setup Time for Repeated Start Condition
0
tHD:DAT
SDA Hold Time from SCL Falling
(Note 10)
0.25
tSU:DAT
SDA Setup Time to SCL Rising
-
tR
Rise Time of Both SDA and SCL Lines
-
tF
Fall Time of Both SDA and SCL Lines
4.0
tSU:STO
Setup Time for Stop Condition
tSP
Maximum Pulse Width of Spike Noise Suppressed by
Input Filter
Power-down & Reset Timing
PDN Pulse Width
(Note 11)
tPD
150
Note 10. Data must be held long enough to bridge the 300 ns transition time of SCL.
Note 11. The AK4120 can be reset by bringing PDN “L” to “H” upon power-up.
Note 12. I
2
C is a registered trademark of Philips Semiconductors.
typ
max
Units
ns
ns
ns
ns
ns
ns
ns
ns
100
-
-
-
-
-
-
-
1.0
0.3
-
30
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
Purchase of Asahi Kasei Microsystems Co., Ltd I C components conveys a license under the Philips
2
2
2
I C patent to use the components in the I C system, provided the system conform to the I C
specifications defined by Philips.
2
MS0134-E-00
-9-
2002/1
AKM [ ASAHI KASEI MICROSYSTEMS ]
