[AK4117]
■ Master Clock Output
The AK4117 has a master clock output pin, MCKO. In PLL mode, PCKS1-0 bits select the MCKO frequency as shown
in Table 2. When MCKO=512fs, MCKO goes to “L” when fs=96kHz and 192kHz. When MCKO=256fs, MCKO goes to
“L” when fs=192kHz. When LP bit is set to “1”, the AK4117 is in low power mode (default). In low power mode, PLL
lock range is up to 48kHz and the MCKO frequency is fixed to 256fs.
In the X’tal mode, XCKS1-0 bits select the ratio of the X’tal frequency to fs (sampling frequency). The DIV bit selects
the ratio (x1 or x1/2) of the MCKO frequency to the X’tal frequency (Table 3).
LP
0
PCKS1
PCKS0
MCKO
512fs
256fs
128fs
N/A
fs [kHz]
0
0
1
1
x
0
1
0
1
x
32 ∼ 48
32 ∼ 96
32 ∼ 192
N/A
1
256fs
Default
32 ∼ 48
Table 2. Master Clock Frequency Select
(PLL mode: Clock operation mode 0, 2(UNLCK=0))
fs [kHz]
X’tal
or
EXT
MCKO
XCKS1 XCKS0
EXTCLK [MHz]
X’tal [MHz]
8.192 11.2896 12.288 24.576
DIV=0 DIV=1
2.048
16
4.096
32
0
0
1
1
0
1
0
1
128fs
256fs
512fs
128fs
256fs
512fs
64fs
128fs
256fs
512fs
64
32
16
8
88.2
44.1
N/A
N/A
96
48
N/A
N/A
192
96
48
8
16
Default
N/A
N/A
8
N/A
1024fs 1024fs
N/A
Table 3. Master Clock Frequency Select
(X’tal mode: Clock operation mode 1, 2(UNLCK=1), 3)
MS0157-E-04
2010/08
- 11 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
