ASAHI KASEI
[AK4114]
PIN/FUNCTION (Continued)
No.
31
Pin Name
PDN
I/O
I
Function
Power-Down Mode Pin
When “L”, the AK4114 is powered-down and reset.
CM0
I
Master Clock Operation Mode 0 Pin in Parallel Mode
32
CDTO
O
Control Data Output Pin in Serial Mode, IIC= “L”.
CAD1
I
Chip Address 1 Pin in Serial Mode, IIC= “H”.
CM1
I
Master Clock Operation Mode 1 Pin in Parallel Mode
33
CDTI
I
Control Data Input Pin in Serial Mode, IIC= “L”.
SDA
I/O
Control Data Pin in Serial Mode, IIC= “H”.
OCKS1
I
Output Clock Select 1 Pin in Parallel Mode
34
CCLK
I
Control Data Clock Pin in Serial Mode, IIC= “L”
SCL
I
Control Data Clock Pin in Serial Mode, IIC= “H”
OCKS0
I
Output Clock Select 0 Pin in Parallel Mode
35
CSN
I
Chip Select Pin in Serial Mode, IIC=”L”.
CAD0
I
Chip Address 0 Pin in Serial Mode, IIC= “H”.
36
INT0
O
Interrupt 0 Pin
37
INT1
O
Interrupt 1 Pin
38
AVDD
I
Analog Power Supply Pin, 3.3V
External Resistor Pin
39
R
-
18kΩ +/-1% resistor should be connected to AVSS externally.
Common Voltage Output Pin
40
VCOM
-
0.47µF capacitor should be connected to AVSS externally.
41
AVSS
I
Analog Ground Pin
Receiver Channel 0 Pin (Internal biased pin)
42
RX0
I
This channel is default in serial mode.
No Connect
43
NC(AVSS)
I
No internal bonding. This pin should be connected to AVSS.
44
RX1
I
Receiver Channel 1 Pin (Internal biased pin)
TEST 1 pin.
45
TEST1
I
This pin should be connected to AVSS.
46
RX2
I
Receiver Channel 2 Pin (Internal biased pin)
No Connect
47
NC(AVSS)
I
No internal bonding. This pin should be connected to AVSS.
48
RX3
I
Receiver Channel 3 Pin (Internal biased pin)
Note 1. All input pins except internal biased pins should not be left floating.
MS0098-E-04
-5-
2004/03
AKM [ ASAHI KASEI MICROSYSTEMS ]
