ASAHI KASEI
[AKD4113-B]
b-2. Set-up of BICK and LRCK input and output
Please select SW 2_7 (DIR_I/O) according to the setup of audio format of AK4113 (Refer to Table 7).
Output signal
SW3_7 (DIR_I/O)
Slave mode
0
Master mode
1
Table 8. DIR_I/O set-up
c.
Set-up of Audio data format
It sets up by SW 1_2, SW 1_3 and SW1_4 in parallel mode. Please set up DIF2-0 bit in serial mode.
DIF2 pin
(SW1_4)
DIF2 bit
0
0
0
0
1
1
1
1
DIF1 pin
(SW1_3)
DIF1 bit
0
0
1
1
0
0
1
1
DIF0 pin
(SW1_2)
DIF0 bit
0
1
0
1
0
1
0
1
LRCK
I/O
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, Left
justified
24bit, I
2
S
24bit, Left
justified
24bit, I
2
S
16bit, Right
justified
18bit, Right
justified
20bit, Right
justified
24bit, Right
justified
24bit, Left
justified
24bit, I
2
S
24bit, Left
justified
24bit, I
2
S
H/L
H/L
H/L
H/L
H/L
L/H
H/L
L/H
O
O
O
O
O
O
I
I
64fs
64fs
64fs
64fs
64fs
64fs
64-
128fs
64-
128fs
BICK
I/O
O
O
O
O
O
O
I
I
Default
Default
Mode
0
1
2
3
4
5
6
7
DAUX
SDTO
Table 9. Audio data format
d.
Set-up of CM1 and CM0
The operation mode of PLL is selected by CM1 and CM0. In parallel mode, it can be selected by SW2_1 and
JP18. In serial mode, it can be selected by CM1-0 bits.
CM1 pin
(SW3_1)
CM1 bit
0
0
1
1
CM0 pin (JP18)
CM0 bit
0 (CM0)
1 (CDTO/CM0=H)
0 (CM0)
-
-
0
1
ON
OFF
ON
ON
ON (Note)
ON
ON
ON
Clock
source
PLL (RX)
X'tal
PLL (RX)
X'tal
SDTO
source
RX
DAUX
RX
DAUX
Default
(UNLOCK)
PLL
X'tal
1 (CDTO/CM0=H)
-
ON
ON
X'tal
DAUX
ON: Oscillation (Power-up), OFF: STOP (Power-Down)
Note: When the X’tal is not used as clock comparison for fs detection (XTL0, 1= “1,1”), the X’tal is OFF.
Table 10. Clock Operation Mode Select
<KM076501>
-4-
2004/11
AKM [ ASAHI KASEI MICROSYSTEMS ]
