ASAHI KASEI
[AKD4113-B]
a-3. Set-up of AK4113 input path
It sets up by SW 1_1 (IPS pin) in parallel mode. Please set up IPS2-0 bits in serial mode.
IPS2 bit
0
0
0
0
1
1
1
1
IPS1 bit
IPS0 bit
INPUT Data
0
0
RX1
0
1
RX2
1
0
RX3
1
1
RX4
0
0
RX5
0
1
RX6
1
0
No use
1
1
No use
Table 4. Recovery Data Select (Serial)
Default
IPS0 pin
INPUT Data
L
RX1
Default
H
RX5
Table 5. Recovery Data Select (parallel mode)
b.
Set-up of clock input and output
The signal level outputted/inputted from PORT2 is 3.3V.
MCLK
SDTO
LRCK
BICK
PORT2
DIR
1
5
GND
GND
GND
Figure 2. PORT2 pin layout
b-1. MCKO1/MCKO2
The output of MCKO1 pin or MCKO2 pin can be selected by JP12. The output frequency of MCKO1/MCKO2
is selected by OCKS 1-0.
Output
JP12
signal
Default
MCKO1
MCKO1
MCKO2
MCKO2
Table 6. MCKO1/MCKO2 set-up
OCKS1 pin
(SW3_2)
OCKS1 bit
0
0
1
1
OCKS0 pin
(SW3_3)
OCKS0 bit
0
1
0
1
(X’tal)
MCKO1
NC
10
GND
6
MCKO2
fs (max)
96 kHz
96 kHz
48 kHz
192 kHz
Default
256fs
256fs
256fs
256fs
256fs
128fs
512fs
512fs
256fs
128fs
128fs
64fs
Table 7. Master Clock Frequency Select
<KM076501>
-3-
2004/11
AKM [ ASAHI KASEI MICROSYSTEMS ]
