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AK4112A 参数 Datasheet PDF下载

AK4112A图片预览
型号: AK4112A
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能96kHz的24bit的DIR [High Feature 96kHz 24bit DIR]
分类和应用:
文件页数/大小: 31 页 / 305 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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ASAHI KASEI  
[AK4112A]  
OPERATION OVERVIEW  
n Non-PCM (AC-3, MPEG, etc.) Stream Detect  
The AK4112A has a Non-PCM steam auto detect function. When the 32bit mode Non-PCM preamble based on Dolby  
“AC-3 Data Stream in IEC958 Interface” is detected, the AUTO goes “H”. The 96bit sync code consists of 0x0000,  
0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the AUTO “H”. Once the AUTO is set  
“H”, it will remain “H” until 4096 frames pass through the chip without additional sync pattern being detected. When  
those preambles are detected, the burst preambles Pc and Pd that follow those sync codes are stored to registers 0DH-  
10H.  
n Clock Recovery and 96kHz Detect  
On chip low jitter PLL has a wide lock range with 22kHz to 108kHz and the lock time is less than 20ms. The 96kHz  
detect output pin FS96 goes “H” when the sampling rate is 88.2kHz or more and “L” at 54kHz or less. In X’tal Mode, the  
FS96 pin outputs the value which is set by XFS96. PLL loses lock when the received sync interval is incorrect.  
n Master Clock  
The AK4112A has two clock outputs, MCKO1 and MCKO2. These clocks are derived from either the recovered clock or  
from the X'tal oscillator. The frequencies of the master clock outputs (MCKO1 & MCKO2) are set by OCKS0 and  
OCKS1 as shown in Table 1. 96kHz sampling is not supported at No.2.  
No. OCKS1 OCKS0  
MCKO1  
256fs  
256fs  
MCKO2  
256fs  
128fs  
X’tal  
256fs  
256fs  
fs (kHz)  
32, 44.1, 48, 96  
32, 44.1, 48, 96  
32, 44.1, 48  
0
1
2
3
0
0
1
1
0
1
0
1
Defalt  
512fs  
256fs  
512fs  
Test Mode  
Table 1. Master clock frequencies select  
n Clock Operation Mode  
The CM0 and CM1 select the clock source of MCKO1/2 and the data source of SDTO via the dedicated pins or the  
control register. In Mode 2, the clock source is switched from PLL to X'tal when PLL goes unlock state. In Mode3, the  
clock source is fixed to X'tal, but PLL is also operating and the recovered data such as C bits can be monitored.  
UNLOCK  
FS96  
RFS96 RX  
XFS96  
RFS96 RX  
XFS96  
XFS96 DAUX  
Mode  
CM1  
CM0  
PLL  
ON  
OFF  
ON  
ON  
ON  
X'tal  
OFF  
ON  
ON  
ON  
ON  
Clock source  
PLL  
SDTO  
Default  
0
1
0
0
0
1
-
-
X'tal  
DAUX  
0
1
-
PLL  
2
3
1
1
0
1
X'tal  
DAUX  
X'tal  
ON: Oscillation (Power-up), OFF: STOP (Power-down)  
Table 2. Clock Operation Mode select  
MS0020-E-00  
2000/3  
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