ASAHI KASEI
[AK4101A]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=4.75~5.25V; C
L
=20pF)
Parameter
Symbol
min
Master Clock Timing
3.584
fCLK
Frequency
Duty Cycle
40
dCLK
LRCK Timing
Frequency
28
fs
Duty Cycle at Slave Mode
45
dLCK
Duty Cycle at Master Mode
Audio Interface Timing
Slave Mode
BICK Period
36
tBCK
BICK Pulse Width Low
15
tBCKL
Pulse Width High
15
tBCKH
15
tLRB
LRCK Edge to BICK “↑”
(Note 5)
15
tBLR
BICK “↑” to LRCK Edge
(Note 5)
8
tSDH
SDTI Hold Time
8
tSDS
SDTI Setup Time
Master Mode
BICK Frequency
fBCK
BICK Duty
dBCK
tMBLR
-20
BICK “↓” to LRCK
tSDH
20
SDTI Hold Time
tSDS
20
SDTI Setup Time
Control Interface Timing
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
50
CDTI Hold Time
tCDH
50
CSN “H” Time
tCSW
520
tCSS
50
CSN “↓” to CCLK “↑”
tCSH
50
CCLK “↑” to CSN “↑”
tDCD
CDTO Delay
tCCZ
CSN “↑” to CDTO Hi-Z
(Note 6)
Power-down & Reset Timing
PDN Pulse Width
tPDW
150
Notes:
5. BICK rising edge must not occur at the same time as LRCK edge.
6. CDTO pin is internally connected to a pull-down resistor.
typ
max
27.648
60
192
55
50
Units
MHz
%
kHz
%
%
ns
ns
ns
ns
ns
ns
ns
64fs
50
20
Hz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
70
MS0250-E-00
-7-
2003/07
AKM [ ASAHI KASEI MICROSYSTEMS ]
