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AK4101A 参数 Datasheet PDF下载

AK4101A图片预览
型号: AK4101A
PDF下载: 下载PDF文件 查看货源
内容描述: QUAD产出192KHZ 24位DIT [QUAD OUTPUTS 192KHZ 24 BIT DIT]
分类和应用: 输出元件
文件页数/大小: 29 页 / 317 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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ASAHI KASEI  
[AK4101A]  
OPERATION OVERVIEW  
n General Description  
The AK4101A is a monolithic CMOS circuit that biphase-encodes and transmits audio data, auxiliary information data  
and etc according to the AES3, IEC60958, S/PDIF and EIAJ CP1201 interface standards. There are four sets of stereo  
channels that can be transmitted simultaneously. The chip accepts audio data and auxiliary information data separately,  
multiplexes and biphase-mark encodes the data internally, and drives it directly or through a transformer to a  
transmission line. There are two modes of operation: asynchronous and synchronous. See section of “Asynchronous  
Mode/ Synchronous Mode”.  
n Initialization  
The AK4101A takes 8 bit clock cycles to initialize after PDN pin goes inactive. Also, for correct synchronization,  
MCLK should be synchronized with LRCK but the phase is not critical.  
n MCLK and LRCK Relationship  
For correct synchronization, MCLK and LRCK should be derived from the same clock signal either directly (as through  
a frequency divider) or indirectly (for example, as through a DSP). The relationship of BICK to LRCK is fixed and  
should not change. If MCLK or LRCK move such that they are shifted (128fs x 3) or more cycles from their initial  
conditions, the chip will reset the internal frame and bit counters. However, control registers are not initialized. The  
following frequencies are supported for MCLK.  
CKS1  
CKS0  
MCLK  
128fs  
256fs  
384fs  
512fs  
fs  
0
0
1
1
0
1
0
1
28k-192kHz  
28k-108kHz  
28k-54kHz  
28k-54kHz  
Table 1. MCLK Frequency  
n Asynchronous Mode/ Synchronous Mode  
1. Asynchronous Mode (software controlled)  
The AK4101A can be configured in the asynchronous mode by connecting the ANS pin to logic “L”. In this mode the  
16 to 24-bit audio samples are accepted through a configured audio serial port, and the channel status and user data  
through a serial control host interface (SCI). The SCI allows access to internal buffer memory and control registers  
which are used to store the channel status and user data. 4bytes per channel of user and channel status is stored. This  
data is multiplexed with the audio data from the audio serial port, the parity bit is generated, and the bit stream is  
biphase-mark encoded and driven through the RS422 line drivers. The CRCC code for the channel status is also  
generated according to the professional mode definition in the AES3 standards. This mode also allows for software  
control for mute, reset, audio format selection, clock frequency settings and output enables, via the serial host interface.  
MS0250-E-00  
2003/07  
- 11 -