ASAHI KASEI
[AK2573A]
8.4 Register
Register memory map is shown in Table 8-6 and 8-7. Register access is limited with WP pin and Operation mode
(refer to Fig 9-1, for more information).
Table 8-6 Register (Device Address = A8h)
Address
Register
Function
Bit Type R/W Remark
R_VRFTRIM[7:4]
R_TEMP_OFFSET[3:0]
R_APC_FF_SET[7:6]
R_APC_FB_SET[5:4]
R_APC_INIT_SET[3]
00h
00h
01h
01h
01h
Oscillator Frequency
Temperature sensor offset
APC FF Setting
APC FB Setting
APC FB Initial Setting
4
4
2
2
1
U
U
U
U
U
R/W
R/W
R/W see Table 4-4
R/W see Table 4-4
R/W 0: No initial Setting
1: Initial Setting
R/W 0: No SFP Support
1: SFP Support
R/W 0: Gain = 1/2
1: Gain = 1
R/W 0: Gain = 1/2
1: Gain = 1
R/W 0: OFF
1: ON
R/W 0: 160ms
1: 2ms
R/W 0: “H”
1: “L”
R/W 00: 1/3, 01: 1/4
10: 1/6, 11: 1/7
R/W see section 6.2
R_SFP[2]
01h
01h
01h
02h
02h
02h
02h
03h
MSA(SFP) Setting
I-DAC1 Gain
1
1
1
U
U
U
U
U
U
U
U
R_DAC1_GAIN[1]
R_DAC2_GAIN[0]
R_TEMP_DET[5]
R_TIMER_OPTALM[4]
R_ALM_POL[3]
R_OPTALM[1:0]
R_TEMP_WIN[6:0]
I-DAC2 Gain
Temperature compensation 1
at shutdown release ON/OFF
Delay time of TXFAULT 1
detection with OPTALM
ALM Polarity
1
2
7
OPTALM Reference Level
Temperature Difference
Detection Level
R_DAC1_FBRT[6:0]
R_DATAALM_MASK[0]
05h
06h
APC FB Ratio for I-DAC1
DATAALM Mask
7
1
U
U
R/W see section 4.3
R/W 0: DATAALM Valid
1: DATAALM Invalid
R/W see section 4.3
R/W see Table 4-2
R/W see Table 4-9
R/(W) see Table 4-9
R/(W) see section 6.2
R_DAC2_FBRT[6:0]
R_PDGAIN[5:0]
R_TEMPALM[6:0]
R_TEMP[6:0]
07h
08h
09h
0Ah
0Bh
APC FB Ratio for I-DAC2
PDGAIN
TEMPALM Level
Detected Temperature
Temperature at Shutdown 7
request
7
6
7
7
U
U
U
U
U
R_TEMP_STDW[6:0]
R_DAC1_FF[7:0]
R_DAC2_FF[7:0]
R_APC_FB[8:0]
R_DAC1_FB[8:0]
R_DAC2_FB[8:0]
R_DAC1[7:0]
R_DAC2[7:0]
R_APC_TRGT[4:0]
R_CURRALM_DAC1[7:4] 16h
R_CURRALM_DAC2[3:0] 16h
R_DUTY[4:0]
AKM Test
0Ch
0Dh
0Eh
11h
12h
13h
14h
15h
I-DAC1 FF
I-DAC2 FF
APC FB
I-DAC1 FB
I-DAC2 FB
I-DAC1
I-DAC2
APC Reference
CURRALM for I-DAC1
CURRALM for I-DAC2
Duty Adjust
Test for AKM
8
8
9
9
9
8
8
5
4
4
5
-
U
U
S
S
S
U
U
U
U
U
U
-
R/W Note 2
R/W Note 3
R/(W) Note 1
R/(W) Note 1
R/(W) Note 1
R/(W) Note 2
R/(W) Note 3
R/W see Table 4-3
R/W see section 5.2
R/W see section 5.2
R/W
17h
18h-
1Dh
-
Note 1: The data format of read / write via ICTM (8bit) is shown in Fig 8-1.
Note 2: R_DAC1 = R_DAC1_FF + R_DAC1_FB, R_DAC1>=0,
Note 3: R_DAC2 = R_DAC2_FF + R_DAC2_FB, R_DAC2 >= 0
2
<MS0189-E-01>
-33-
2004/5
AKM [ ASAHI KASEI MICROSYSTEMS ]
