ASAHI KASEI
Figure 4-3 APC_FB Functional Block Diagram
[AK2572]
APC_FF
+
DAC
R_TEMP
TEMPSENS
ADC
EEPROM
R_DAC2
R_DAC1/R_DAC3
APC_FB Initial value setting is possible in
response to temperature at the start-up
PDMON
R_APC_FBIV
A proper APC_FB initial value setting
can shorten the start-up time
Monitor
PD
512kHz [Typ.]
DIGITAL FILTER
PDIN
vpd
PDGAIN
R_APC_FB
APC_
comp_out
1/N
1/s
COMP
Rpd
Dispersion of monitor PD current
is cancelled and a normalized
voltage is output on PDMON-pin
Cpd
DAC code is incremented or
decremented by 1 LSB step in order
to prevent the excessive current
RE_APC_TRGT
DAC_APC
vapc_ref
4.2.1 APC_FB Circuit Block Diagram
The operation of each block is shown in Table 4-1.
Table 4-1 APC_FB Block Diagram Descriptions
Block
Function
Note
Amplified PDIN voltage by gain value (vpd) and APC target value (vapc_ref) are
compared and if “vpd＜vapc_ref”, UP (increment) request or if “vpd≧vapc_ref”, DOWN
(decrement) request is output on digital filter. The comparison is made at 512 kHz [Typ.].
APC_
COMP
DIGITAL From the APC_COMP result, R_APC_FB value is calculated so that vpd and vapc_ref
FILTER are equal.
Amplified PDIN voltage by gain value is output on PDMON-pin. Input range is 0.08 V ~
PDGAIN 2.5V. Adjust the gain so that PDMON output voltage is equal to 1.0V [Typ.]. When to set
a normalized voltage lower than 1.0 V, adjust it by utilizing external resistor-divider etc..
APC reference voltage (vapc_ref) is output. Output voltage is adjustable by
DAC_APC RE_APC_TRGT setting. APC_FB operates such that the amplified PDIN voltage by gain
value equals to DAC_APC output.
4.2.2 Normalization of PD Monitoring Current
A monitor PD current is converted into average voltage by an external resistor and a capacitor and it is fed on
PDIN-pin. Input voltage range of PDIN at initial adjustment is listed in Table 4-2.
PDIN voltage is amplified by gain value at PDGAIN block and it is output on PDMON-pin. Adjust PDGAIN so
that output voltage on PDMON-pin is 1.0 V [Typ.]. In Table 4-3, adjustable range of RE_PDGAIN is listed.
When a lower than 1.0 V [Typ.] is required as a normalized voltage, voltage-divide it by an external
resistor-divider etc..
Table 4-2 PDIN Input Condition
Item
PDIN input voltage
Min.
0.08V
Max.
2.5V
Note
Table 4-3 PDGAIN Setting
Set-up gain ［Typ.］
RE_PDGAIN
00 0000 (00h)
00 0001 (01h)
･･･
Note
23.5 dB
23.0 dB
･･･
0.5 dB / step
11 1110 (3Eh)
11 1111 (3Fh)
- 7.5 dB
- 8.0 dB
-16-
<MS0290-E-01>
2004/8
AKM [ ASAHI KASEI MICROSYSTEMS ]
