ASAHI KASEI
[AK2346B]
2) MSK Demodulator control flow
MSK data receiver, Demodulator interfaces with RXIN, RDF/FD, SCLK, DI/O and DIR pins and
also FCLN, FSL, and RXSW registers as below.
: Setting flame detect (FD) enable
FCLN=0
FSL=0
: Setting for FD signal put out from
RDF/FD pin.
N
: Synchronized frame pattern
detect or not ?
RDF/FD “Low”
Y
: FD is disable automatically
: Receive audio mute
FCLN=1 (automatically)
RXSW=0
FSL=1
: Setting for received flag (RDF) signal
put out from RDF/FD pin.
N
N
RDF/FD “Low”
Y
: 8 bit data received or not ?
Reading receive data
Have all receive data
been read out?
: Having read 8bit data, RDF/FD pin
puts out high level.
Y
FCLN=0
: Waiting for the next synchronized
flame.
(1)
(2)
(3)
Setting FCLN=0 and FSL=0 for flame detect mode and also SCLK pin sets high level
and DIR pin sets low level, RDF/FD pin puts out high level and wait for synchronized frame.
(Point A)
After a synchronized frame is detected, RDF/FD pin works as frame detect (FD) mode.
FD goes to low level during the period of time “T”, then FCLN is sets to “1” automatically.
(Point B, C)
Monitoring low level of RDF/FD pin, set RXSW=0 for audio signal mute. Then set FSL=1 for
received flag (RDF), signal put out from RDF/FD pin.
(Between C and D)
MS1409-E-00
2012/05
- 24 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
