ASAHI KASEI
FUNCTIONAL
DISCRIPTIONS
[AK2307/LV]
1. SERIAL INTERFACE
The internal registers can be read/written via serial CPU interface which consists of SCLK, DATA, and CSN
pin.
1 word consists of 16bits. The first 3bits are the instruction code which specifies read or write.
The following 4bits specify the address. The rest of 8bits are the data stored in the internal registers.
Table1-A CPU I/F ADDRESS/DATA STRUCTURE
B15 B14 B13 B12 B11 B10
B9
B8
I2
I1
I0
A3
A2
A1
A0
*
*
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
B0
D0
Instruction code
(3 bit )
Address
(4bit)
Data for internal registers
(8bit)
*)Dummy bit for adjusting the I/O timing when reading register.
Table1-B
INSTRUCTION CODE
I2
1
1
I1
1
1
Others
I0
0
1
Read/Write
Read
Write
No action
1-2
Timing of the Serial Interface
SCLK and DATA timing in WRITE/READ operation
(1) Input data are loaded into the internal shift register at the rising edge of SCLK.
(2) The rising edge of SCLK is counted after the falling edge of CSN.
(3) When CSN is “L” and more than 16 SCLK pulses:
th
[WRITE]
Data are loaded into the internal register at the rising edge of the SCLK 16 pulse.
th
[READ]
DATA pin becomes an input pin at the falling edge of the SCLK 16 pulse.
CSN timing and WRITE/READ CANCELLATION
(1) WRITE is cancelled when CSN goes up before the rising edge of the SCLK 16 pulse.
th
(2) READ is cancelled when CSN goes up before the falling edge of the SCLK 16 pulse.
th
SERIAL WRITE/READ ACCESS timing (SERIAL ACCESS MODE)
(1) Serial write and read operation will be done by feeding the another 16 SCLK pulse and
st
data after 1 write or read operation.
st
nd
(2) It is not necessary to make CSN high between 1 operation and 2 operation.
MS0190-E-05
6
2005/12
AKM [ ASAHI KASEI MICROSYSTEMS ]
