[AK1572]
Reference clock
Phase Comparison signal
Divided signal of RF signal
PFD output signal
T
ignore
This is ignored because it
cannot be sampled.
This is ignored
because it cannot
be sampled.
Valid
Valid
The [LD] pin outputs will be HIGH
when a phase error which is smaller
than T is detected for N times
LD output
Case of “R > 1”
Fig6. .Digital Lock Detect Operations
Unlock⇒Lock
Unlock(LD=LOW)
Flag=0
No
Phase Error < T
Yes
Flag=Flag+1
No
Flag>N
Yes
Lock(LD=HIGH)
MS1551-E-00
23
2013/8