[AK1541]
2. Serial Interface Timing
<Write-In Timing>
Tlesu
LE
(Input)
Tch
CLK
(Input)
Tsu
DATA
(Input)
Thd
Tcl
Tle
Tcsu
D19
D18
D0
A3
A2
A1
A0
D19
Fig. 3 Serial Interface Timing
Table 5 Serial Interface Timing
Parameter
Clock L level hold time
Clock H level hold time
Clock setup time
Data setup time
Data hold time
LE Setup Time
LE Pulse Width
Symbol
Tcl
Tch
Tcsu
Tsu
Thd
Tlesu
Tle
Min.
40
40
20
20
20
20
40
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
Remarks
Note 1)
LE pin has to be set “Low” after register data setting completed. If LE pin keeps “High” with CLK operation, the
register may not be guaranteed proper setting.
Note 2) While LE pin is setting “Low”, 24 iteration clocks have to be set with CLK pin. If 25 or larger clocks are set, the
last 24 clocks synchronized data are valid.
MS1043-E-05
8
2013/03