[AK1541]
14. Typical Evaluation Board Schematic
RFOUT
AK1541
18Ω
18Ω
Loop Filter
100pF
R3
100pF
VCO
CP
REFIN
C1
R2'
R2
18Ω
C3
VREF1
VREF2
220nF
SWIN
CPZ
C2
220nF
100pF
100pF
RFINP
RFINN
BIAS
27kΩ
51Ω
Fig. 14 Typical Evaluation Board Schematic
The input voltage from the [CPZ] pin is used in the internal circuit. The [CPZ] pin must not be open even when the fast
lockup feature is unused. For the output destination from the [CPZ] pin, see “P.12 Fig.5 Loop Filter Schematic”. The
[SWIN] pin could be open even when the first lockup feature is not used.
R2 and R2’ are connected in parallel with internal switch in Fast Lockup. These R2 and R2’ parallel resistance value is
required for calculating loop bandwidth and phase margin in Fast Lockup. An On resistance value of the internal switch is
150Ω for reference.
MS1043-E-05
32
2013/03
AKM [ ASAHI KASEI MICROSYSTEMS ]
