A6110
AiT Semiconductor Inc.
www.ait-ic.com
LOW DROPOUT VOLTAGE REGULATOR
1A HIGH PSRR CMOS,LINEAR REGULATOR
capacitance can be increased without limit. The input capacitor must be located a distance of not more than
0.5 inch from the input pin of the IC and returned to a clean analog ground. Any good quality ceramic or
tantalum can be used for this capacitor. The capacitor with larger value and lower ESR (equivalent series
resistance) provides better PSRR and line-transient response. The output capacitor must meet both
requirements for minimum amount of capacitance and ESR in all LDO applications. The A6110 is designed
specifically to work with low ESR ceramic output capacitor in space-saving and performance consideration. In
the A6110, phase compensation is made with the output capacitor for securing stable operation even if the
load current is varied. For this purpose, use a 2.2uF capacitor between VOUT pin and GND pin as close as
possible.
Load-Transient Considerations
The A6110 load-transient response graphs show two components of the output response: a DC shift from the
output impedance due to the load current change, and the transient response. The DC shift is quite small due
to the excellent load regulation of the IC. Typical output voltage transient spike for a step change in the load
current from 0mA to 50mA is tens of mV, depending on the ESR of the output capacitor. Increasing the output
capacitor's value and decreasing the ESR attenuates the overshoot.
Input-Output (Dropout) Voltage
A regulator's minimum input-output voltage differential (or dropout voltage) determines the lowest usable
supply voltage. In battery-powered systems, this will determine the useful end-of-life battery voltage. Because
the A6110 uses a P-Channel MOSFET pass transistor, the dropout voltage is a function of drain-to-source on
resistance [RDS(ON)] multiplied by the load current.
Layout Considerations
To improve AC performance such as PSRR, output noise, and transient response, it is recommended that the
PCB be designed with separate ground planes for VDD and VOUT, with each ground plane connected only at
the GND pin of the device. Make VDD and GND lines sufficiently wide. If their impedance is high, noise pickup
or unstable operation may result. Connect a capacitor C1 between VDD and GND pin, as close as possible to
the pins. Set external components, especially the output capacitor C2, as close as possible to the IC, and
make wiring as short as possible.
REV1.7
- OCT 2010 RELEASED, APR 2016 UPDATAED -
- 10 -
AITSEMI [ AiT Semiconductor ]
