A24C16
AiT Semiconductor Inc.
www.ait-ic.com
MEMORY EEPROM
16k BITS (2048 X 8) TWO-WIRE SERIAL
BUS TIMING
Figure 10 SCL: Serial Clock, SDA: Serial Data I/O
WRITE CYCLE TIMING
Figure 11 SCL: Serial Clock, SDA: Serial Data I/O
NOTE: The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
REV2.0
- SEP 2008 RELEASE, NOV 2016 UPDATED -
- 13 -