A24C1024
TWO-WIRE SERIAL EEPROM
1024K (131.072 X 8)
AiT Semiconductor Inc.
www.ait-ic.com
DETAILED INFORMATION
Device Operation
The A24C1024 serial interface supports communications using industrial standard 2-wire bus protocol, such
as I2C.
2-WIRE Bus
The two-wire bus is defined as Serial Data (SDA), and Serial Clock (SCL). The protocol defines any device
that sends data onto the SDA bus as a transmitter, and the receiving devices as receivers. The bus is
controlled by Master device that generates the SCL, controls the bus access, and generates the Start and
Stop conditions. The A24C1024 is the Slave device.
The Bus Protocol
Data transfer may be initiated only when the bus is not busy. During a data transfer, the SDA line must remain
stable whenever the SCL line is high. Any changes in the SDA line while the SCL line is high will be
interpreted as a Start or Stop condition.
The state of the SDA line represents valid data after a Start condition. The SDA line must be stable for the
duration of the High period of the clock signal. The data on the SDA line may be changed during the Low
period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start
condition and terminated by a Stop condition.
Start Condition
The Start condition precedes all commands to the device and is defined as a High to Low transition of SDA
when SCL is high. The EEPROM monitors the SDA and SCL lines and will not respond until the Start
condition is met.
Stop Condition
The Stop condition is defined as a Low to High transition of SDA when SCL is high. All operations must end
with a Stop condition.
Acknowledge
After a successful data transfer, each receiving device is required to generate an ACK. The Acknowledging
device pulls down the SDA line.
REV1.0
- JUN 2014 RELEASED -
- 7 -
AITSEMI [ AiT Semiconductor ]
