AiT Semiconductor Inc.
A24C08
www.ait-ic.com
MEMORY EEPROM
8k BITS (1024X8) TWO-WIRE SERIAL
3. Device Addressing
The 8k EEPROM devices all require an 8-bit device address word following a start condition to enable the
chip for a read or write operation (see Figure 4 on page11)
The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as
shown. This is common to all the Serial EEPROM devices.
The 8k EEPROM uses A2 device address bits to allow two devices on the same bus. This bit must be
compared to their corresponding hardwired input pins. The A2 pin uses an internal proprietary circuit that
biases them to a logic low condition if the pin is allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit
is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will
return to a standby state.
DATA SECURITY: The A24C08 has a hardware data protection scheme that allows the user to write protect
the entire memory when the WP pin is at VCC.
4. Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in
the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the
addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this
time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are
disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 5 on
page11).
PAGE WRITE: The 8k devices are capable of 16-byte page writes.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after
the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the
microcontroller can transmit up to fifteen more data words. The EEPROM will respond with a "0" after each
data word received. The microcontroller must terminate the page write sequence with a stop condition (see
Figure 6 on page11).
The data word address lower four bits are internally incremented following the receipt of each data word. The
higher data word address bits are not incremented, retaining the memory page row location. When the word
address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the
same page. If more than sixteen data words are transmitted to the EEPROM, the data word address will "roll
over" and previous data will be overwritten.
REV3.0
- SEP 2008 RELEASED, OCT 2018 UPDATED -
- 8 -
AITSEMI [ AiT Semiconductor ]
