AT1367A/B/C/D
Preliminary Product Information
1MHz, 800mA Synchronous Buck Converter
With Power Good Detector & LDO
efficiency when selecting an inductor. The inductor is selected to limit the ripple
current to some predetermined value, typically 20~40% of the full load current at the
maximum input voltage. The formula of inductance value is as below:
∆IL = 0.2 ~ 0.4× IOUT (MAX )
VOUT
f ×∆IL
VOUT
VIN
L =
1−
∆IL
2
(VIN −VOUT )×tON
2× L
IPK = IO +
= IO +
Power Good Indicator with Adjustable Time Delay
The PG and /PG pin terminal is an open drain output of N-MOS. Connect a resistor
from PG and /PG pin to VCC or OUT1 to create a logic signal. If OUT1 pin is less
than 2.97V (typ.) this pin is pulled to ground. When OUT1 pin is above 2.97V and
with a delay time this pin is open. PG and /PG pin is forced low when in UVLO. The
formula of adjustable delay time is as below :
0.8
IDELAY
delay − time = C ×
The Dissipation
The power loss is given by:
P
= IO2UT1 × RDS(ON)−P × D + IO2UT1 × RDS(ON)−N ×(1− D) +VIN × IOUT1 ×(tr + t f )× fs + Is ×VIN
LOSS(DC−DC)
P
= IOUT 2 ×(VOUT1 −VOUT 2 )
LOSS(LDO)
TJ (MAX ) = TA +θJA × (PLOSS (DC−DC) + PLOSS (LDO)
)
7F, No.9, Park Avenue II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C.
Tel: 886-3-563-0878
Fax: 886-3-563-0879
WWW: http://www.aimtron.com.tw
Email: service@aimtron.com.tw
3/2/2006 REV:1.2
10
AIMTRON [ AIMTRON TECHNOLOGY ]
