AT1361
1MHz,1A Synchronous Buck Converter
PC Board Layout
1. The most critical aspect of the layout is the placement of the input capacitor C1. It must
be placed as close as possible to the AT1361 to reduce the input ripple voltage.
2. Power loops on the input and output of the converter should be laid out with the shortest
and widest traces possible. The longer and narrower the trace, the higher resistance and
inductance it will have. The length of traces in series with the capacitors increases its
ESR and ESL and reduces their effectiveness at high frequency.
3. The FB pin should connect to feedback resistors directly. And the route should be away
from the noise source, such as inductor of SW line.
4. Grounding all components at the same point may effectively reduce the occurrence of
loop.
7F, No.9, PARK AVENUE II, Science-Based Industrial Park, Hsinchu 300,Taiwan, R.O.C.
Tel: 886-3-563-0878
1/11/2008 REV:1.0
Fax: 886-3-563-0879
WWW: http://www.aimtron.com.tw
Email:service@aimtron.com.tw
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AIMTRON [ AIMTRON TECHNOLOGY ]
